168 lines
5.3 KiB
Python
168 lines
5.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Leds
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("user_led", 0, Pins("F16"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("F17"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("G15"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("K14"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("G14"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("J15"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("J14"), IOStandard("LVCMOS33")),
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("dac", 0,
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Subsignal("data",
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Pins("M19 M20 L19 L20 K19 J19 J20 H20 G19 G20 F19 F20 D20 D19"),
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Drive(4), Misc("SLEW SLOW")),
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Subsignal("wrt", Pins("M17"), Drive(8), Misc("SLEW FAST")),
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Subsignal("sel", Pins("N16"), Drive(8), Misc("SLEW FAST")),
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Subsignal("clk", Pins("M18"), Drive(8), Misc("SLEW FAST")),
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Subsignal("rst", Pins("N15"), Drive(8), Misc("SLEW FAST")),
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IOStandard("LVCMOS33"),
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),
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("pwm_dac", 0, Pins("T10"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("pwm_dac", 1, Pins("T11"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("pwm_dac", 2, Pins("P15"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("pwm_dac", 3, Pins("U13"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("daisy", 0,
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Subsignal("io0_p", Pins("T12")),
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Subsignal("io0_n", Pins("U12")),
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Subsignal("io1_p", Pins("U14")),
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Subsignal("io1_n", Pins("U15")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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("daisy", 1,
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Subsignal("io0_p", Pins("P14")),
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Subsignal("io0_n", Pins("R14")),
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Subsignal("io1_p", Pins("N18")),
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Subsignal("io1_n", Pins("P19")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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]
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_io_14 = [
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# Clk / Rst
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("clk125", 0,
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Subsignal("p", Pins("U18")),
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Subsignal("n", Pins("U19")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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("adc", 0,
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Subsignal("data_a",
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Pins("Y17 W16 Y16 W15 W14 Y14 W13 V12 V13 T14 T15 V15 T16 V16")),
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Subsignal("data_b",
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Pins("R18 P16 P18 N17 R19 T20 T19 U20 V20 W20 W19 Y19 W18 Y18")),
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Subsignal("cdcs", Pins("V18")),
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IOStandard("LVCMOS18"),
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),
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]
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_io_16 = [
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# Clk / Rst
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("clk122", 0,
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Subsignal("p", Pins("U18")),
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Subsignal("n", Pins("U19")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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("adc", 0,
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Subsignal("data_a",
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Pins("V17 U17 Y17 W16 Y16 W15 W14 Y14 W13 V12 V13 T14 T15 V15 T16 V16")),
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Subsignal("data_b",
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Pins("T17 R16 R18 P16 P18 N17 R19 T20 T19 U20 V20 W20 W19 Y19 W18 Y18")),
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Subsignal("cdcs", Pins("V18")),
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IOStandard("LVCMOS18"),
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),
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]
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_ps7_io = [
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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_uart_io = [
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("usb_uart", 0,
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Subsignal("tx", Pins("E1:3")),
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Subsignal("rx", Pins("E1:4")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("E1", "- - G17 G18 H16 H17 J18 H18 K17 K18 L14 L15 L16 L17 K16 J16 M14 M15 - - - - - - - -"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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def __init__(self, board="redpitaya14"):
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if board == "redpitaya14":
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device = "xc7z010clg400-1"
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extension = _io_14
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self.default_clk_name = "clk125"
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self.default_clk_freq = 125e6
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else:
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device = "xc7z020clg400-1"
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extension = _io_16
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self.default_clk_name = "clk122"
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self.default_clk_freq = 122e6
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self.default_clk_period = 1e9/self.default_clk_freq
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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self.add_extension(extension)
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self.add_extension(_ps7_io)
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self.add_extension(_uart_io)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
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self.default_clk_period)
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