191 lines
7.6 KiB
Python
Executable File
191 lines
7.6 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import fomu_pvt
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from litex.soc.cores.ram import Up5kSPRAM
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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assert sys_clk_freq == 12e6
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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# # #
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# Clk/Rst
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clk48 = platform.request("clk48")
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platform.add_period_constraint(clk48, 1e9/48e6)
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# USB PLL
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self.submodules.pll = pll = iCE40PLL()
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#self.comb += pll.reset.eq(self.rst) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
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pll.clko_freq_range = ( 12e6, 275e9) # FIXME: improve iCE40PLL to avoid lowering clko_freq_min.
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.specials += AsyncResetSynchronizer(self.cd_usb_12, ~por_done | ~pll.locked)
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self.specials += AsyncResetSynchronizer(self.cd_usb_48, ~por_done | ~pll.locked)
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# Sys Clk
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self.comb += self.cd_sys.clk.eq(self.cd_usb_12.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq=int(12e6),
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with_led_chaser=True, **kwargs):
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kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM
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platform = fomu_pvt.Platform()
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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# Serial -----------------------------------------------------------------------------------
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# FIXME: do proper install of ValentyUSB.
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os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
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sys.path.append("valentyusb")
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Fomu",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=128*kB)
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self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
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self.bus.add_region("sram", SoCRegion(
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origin = self.bus.regions["psram"].origin + 0*kB,
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size = 64*kB,
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linker = True)
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)
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if not self.integrated_main_ram_size:
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self.bus.add_region("main_ram", SoCRegion(
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origin = self.bus.regions["psram"].origin + 64*kB,
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size = 64*kB,
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linker = True)
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)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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# lambdas for lazy module instantiation.
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spi_flash_modules = {
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"AT25SF161": lambda: AT25SF161( Codes.READ_1_1_4),
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"GD25Q16C": lambda: GD25Q16C( Codes.READ_1_1_1),
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"MX25R1635F": lambda: MX25R1635F(Codes.READ_1_1_4),
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"W25Q128JV": lambda: W25Q128JV( Codes.READ_1_1_4),
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}
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self.add_spi_flash(mode="4x", module=spi_flash_modules[spi_flash_module](), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# Flash --------------------------------------------------------------------------------------------
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def flash(build_dir, build_name, bios_flash_offset):
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from litex.build.dfu import DFUProg
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prog = DFUProg(vid="1209", pid="5bf0")
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bitstream = open(f"{build_dir}/gateware/{build_name}.bin", "rb")
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bios = open(f"{build_dir}/software/bios/bios.bin", "rb")
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image = open(f"{build_dir}/image.bin", "wb")
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# Copy bitstream at 0.
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assert bios_flash_offset >= 128*kB
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for i in range(0, bios_flash_offset):
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b = bitstream.read(1)
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if not b:
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image.write(0xff.to_bytes(1, "big"))
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else:
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image.write(b)
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# Copy bios at bios_flash_offset.
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for i in range(0, 32*kB):
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b = bios.read(1)
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if not b:
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image.write(0xff.to_bytes(1, "big"))
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else:
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image.write(b)
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bitstream.close()
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bios.close()
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image.close()
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prog.load_bitstream(f"{build_dir}/image.bin")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Fomu")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
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target_group.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
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target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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dfu_flash_offset = 0x40000
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soc = BaseSoC(
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bios_flash_offset = dfu_flash_offset + int(args.bios_flash_offset, 0),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.flash:
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flash(builder.output_dir, soc.build_name, int(args.bios_flash_offset, 0))
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if __name__ == "__main__":
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main()
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