201 lines
7.9 KiB
Python
Executable File
201 lines
7.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.uart import *
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from litex.soc.integration.cpu_interface import get_csr_header
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litex_boards.platforms import aller
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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clk100 = platform.request("clk100")
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self.submodules.pll = pll = S7PLL()
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# AllerSoC -----------------------------------------------------------------------------------------
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class AllerSoC(SoCSDRAM):
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SoCSDRAM.mem_map["csr"] = 0x80000000
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SoCSDRAM.mem_map["rom"] = 0x20000000
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def __init__(self, platform, with_pcie_uart=True):
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sys_clk_freq = int(100e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, sys_clk_freq,
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csr_data_width = 32,
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integrated_rom_size = 0x10000,
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integrated_sram_size = 0x10000,
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integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests
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ident = "Aller LiteX Test SoC", ident_version=True,
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with_uart=not with_pcie_uart)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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self.add_csr("crg")
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.add_csr("dna")
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.add_csr("xadc")
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6)
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self.add_csr("ddrphy")
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sdram_module = MT41J128M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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self.pcie_phy.cd_pcie.clk.attr.add("keep")
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platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]")
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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# pcie endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, base_address=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering=True, buffering_depth=1024, with_loopback=True)
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self.add_csr("pcie_dma")
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# pcie msi
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.msis = {
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"DMA_WRITER": self.pcie_dma.writer.irq,
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"DMA_READER": self.pcie_dma.reader.irq
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}
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for i, (k, v) in enumerate(sorted(self.msis.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# pcie_uart
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if with_pcie_uart:
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class PCIeUART(Module, AutoCSR):
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def __init__(self, uart):
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self.rx_valid = CSRStatus()
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self.rx_ready = CSR()
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self.rx_data = CSRStatus(8)
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self.tx_valid = CSR()
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self.tx_ready = CSRStatus()
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self.tx_data = CSRStorage(8)
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# # #
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# cpu to pcie
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self.comb += [
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self.rx_valid.status.eq(uart.sink.valid),
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uart.sink.ready.eq(self.rx_ready.re),
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self.rx_data.status.eq(uart.sink.data),
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]
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# pcie to cpu
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self.sync += [
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If(self.tx_valid.re,
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uart.source.valid.eq(1)
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).Elif(uart.source.ready,
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uart.source.valid.eq(0)
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)
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]
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self.comb += [
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self.tx_ready.status.eq(~uart.source.valid),
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uart.source.data.eq(self.tx_data.storage)
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]
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uart_interface = RS232PHYInterface()
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self.submodules.uart = UART(uart_interface)
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self.add_csr("uart")
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self.add_interrupt("uart")
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self.submodules.pcie_uart = PCIeUART(uart_interface)
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self.add_csr("pcie_uart")
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# Leds -------------------------------------------------------------------------------------
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# led blinking (sys)
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sys_counter = Signal(32)
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self.sync.sys += sys_counter.eq(sys_counter + 1)
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pcie_counter = Signal(32)
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self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
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self.comb += [
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platform.request("user_led", 0).eq(~self.pcie_phy._lnk_up.status),
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platform.request("user_led", 1).eq(~pcie_counter[26]),
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platform.request("user_led", 2).eq(~sys_counter[26]),
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]
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def generate_software_header(self, filename):
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csr_header = get_csr_header(self.csr_regions,
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self.constants,
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with_access_functions=False)
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tools.write_to_file(filename, csr_header)
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# Build --------------------------------------------------------------------------------------------
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def main():
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platform = aller.Platform()
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soc = AllerSoC(platform)
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builder = Builder(soc, output_dir="aller", csr_csv="aller/csr.csv",
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compile_gateware=not "no-compile" in sys.argv[1:])
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vns = builder.build(build_name="aller")
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soc.generate_software_header("aller/csr.h")
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if __name__ == "__main__":
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main()
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