108 lines
3.6 KiB
Python
108 lines
3.6 KiB
Python
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# clock / reset
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("clk100", 0, Pins("K23"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("N5"), IOStandard("LVCMOS33")),
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# led
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("rgb_led", 0,
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Subsignal("r", Pins("U21")),
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Subsignal("g", Pins("W21")),
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Subsignal("b", Pins("T24")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 1,
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Subsignal("r", Pins("T23")),
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Subsignal("g", Pins("R21")),
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Subsignal("b", Pins("T22")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 2,
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Subsignal("r", Pins("P21")),
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Subsignal("g", Pins("R23")),
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Subsignal("b", Pins("P22")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 3,
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Subsignal("r", Pins("K21")),
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Subsignal("g", Pins("K24")),
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Subsignal("b", Pins("M21")),
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IOStandard("LVCMOS33"),
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),
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# serial
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("serial", 0,
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Subsignal("rx", Pins("R26"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("R24"), IOStandard("LVCMOS33")),
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),
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# ddram
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("ddram", 0,
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Subsignal("a", Pins(
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"T5 M3 L3 V6 K2 W6 K3 L1",
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"H2 L2 N1 J1 M1 K1"),
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IOStandard("SSTL15_I")),
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Subsignal("ba", Pins("U6 N3 N4"), IOStandard("SSTL15_I")),
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Subsignal("ras_n", Pins("T3"), IOStandard("SSTL15_I")),
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Subsignal("cas_n", Pins("P2"), IOStandard("SSTL15_I")),
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Subsignal("we_n", Pins("R3"), IOStandard("SSTL15_I")),
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Subsignal("dm", Pins("U4 U1"), IOStandard("SSTL15_I")),
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Subsignal("dq", Pins(
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"T4 W4 R4 W5 R6 P6 P5 P4",
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"R1 W3 T2 V3 U3 W1 T1 W2",),
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IOStandard("SSTL15_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("V4 V1"), IOStandard("SSTL15D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("H3"), IOStandard("SSTL15D_I")),
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Subsignal("cke", Pins("P1"), IOStandard("SSTL15_I")),
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Subsignal("odt", Pins("P3"), IOStandard("SSTL15_I")),
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Misc("SLEWRATE=FAST"),
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),
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# ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("A12")),
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Subsignal("rx", Pins("E11")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("C13")),
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Subsignal("mdio", Pins("A13")),
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Subsignal("mdc", Pins("C11")),
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Subsignal("rx_ctl", Pins("A11")),
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Subsignal("rx_data", Pins("B11 A10 B10 A9"), Misc("PULLMODE=UP")), # RGMII mode - Advertise all capabilities.
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Subsignal("tx_ctl", Pins("C9")),
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Subsignal("tx_data", Pins("D8 C8 B8 A8")),
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IOStandard("LVCMOS33")
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),
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]
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG554I", _io, _connectors, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_ecpix5.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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