160 lines
6.3 KiB
Python
Executable File
160 lines
6.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 John Simons <jammsimons@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import alinx_axau15
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT40A512M16
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from litedram.phy import usddrphy
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from liteeth.phy.usrgmii import LiteEthPHYRGMII
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from litepcie.phy.usppciephy import USPHBMPCIEPHY # FIXME: Use proper name.
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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# Clk.
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clk200 = platform.request("clk200")
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# PLL.
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# IDelayCtrl.
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self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_sys4x, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6),
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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remote_ip = None,
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with_led_chaser = True,
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with_pcie = False,
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**kwargs):
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platform = alinx_axau15.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXAU15", **kwargs)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT40A512M16(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
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speed = "gen3",
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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tx_delay = 1e-9,
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rx_delay = 1e-9,
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usp = True
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)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, remote_ip=remote_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=alinx_axau15.Platform, description="LiteX SoC on AXAU15.")
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parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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remote_ip = args.remote_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_pcie = args.with_pcie,
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**parser.soc_argdict
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)
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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