159 lines
5.2 KiB
Python
159 lines
5.2 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Basel Sayeh <Basel.Sayeh@hotmail.com>
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("B14"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("AD23"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("AD24"), IOStandard("3.3-V LVTTL")),
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# SPIFlash (W25Q64)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("D5")),
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Subsignal("clk", Pins("F6")),
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Subsignal("mosi", Pins("E6")),
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Subsignal("miso", Pins("D6")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("J23"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"L25 L26 M25 M26 N22 N23 N24 M22",
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"M24 L23 K26 L24 K23")),
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Subsignal("ba", Pins("J25 J26")),
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Subsignal("cs_n", Pins("H26")),
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Subsignal("cke", Pins("K24")),
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Subsignal("ras_n", Pins("H25")),
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Subsignal("cas_n", Pins("G26")),
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Subsignal("we_n", Pins("G25")),
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Subsignal("dq", Pins(
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"B25 B26 C25 C26 D25 D26 E25 E26",
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"H23 G24 G22 F24 F23 E24 D24 C24")),
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Subsignal("dm", Pins("F26 H24")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U5 and J3 is U4
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_connectors = [
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("J2", {
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# odd row even row
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7: "AF24", 8: "AF25",
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9: "AC21", 10: "AD21",
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11: "AE23", 12: "AF23",
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13: "AE22", 14: "AF22",
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15: "AD20", 16: "AE21",
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17: "AF20", 18: "AF21",
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19: "AE19", 20: "AF19",
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21: "AC19", 22: "AD19",
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23: "AE18", 24: "AF18",
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25: "AC18", 26: "AD18",
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27: "AE17", 28: "AF17",
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29: "AC17", 30: "AD17",
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31: "AF15", 32: "AF16",
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33: "AC16", 34: "AD16",
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35: "AE14", 36: "AE15",
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37: "AC15", 38: "AD15",
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39: "AC14", 40: "AD14",
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41: "AF11", 42: "AF12",
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43: "AC10", 44: "AD10",
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45: "AE9", 46: "AF9",
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47: "AF7", 48: "AF8",
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49: "AE7", 50: "AF6",
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51: "AE5", 52: "AE6",
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53: "AD5", 54: "AD6",
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55: "AF4", 56: "AF5",
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57: "AD3", 58: "AE3",
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59: "AC4", 60: "AD4",
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}),
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("J3", {
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# odd row even row
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7: "C21", 8: "B22",
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9: "B23", 10: "A23",
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11: "B21", 12: "A22",
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13: "C19", 14: "B19",
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15: "A21", 16: "A20",
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17: "A19", 18: "A18",
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19: "C17", 20: "B18",
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21: "C16", 22: "B17",
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23: "A17", 24: "A16",
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25: "B15", 26: "A15",
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27: "C15", 28: "C14",
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29: "C13", 30: "B13",
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31: "C12", 32: "C11",
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33: "A13", 34: "A12",
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35: "B11", 36: "A11",
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37: "B10", 38: "A10",
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39: "C10", 40: "B9",
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41: "A9", 42: "A8",
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43: "A7", 44: "A6",
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45: "B7", 46: "B6",
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47: "B5", 48: "A5",
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49: "B4", 50: "A4",
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51: "C5", 52: "C4",
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53: "A3", 54: "A2",
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55: "B2", 56: "B1",
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57: "D1", 58: "C1",
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59: "E2", 60: "E1",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("user_led", 0, Pins("A25"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("A24"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
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),
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]
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def __init__(self, toolchain="quartus", with_daughterboard=False):
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device = "EP4CGX150DF27I7"
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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else:
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io += self.core_resources
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AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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if with_daughterboard:
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# an ethernet pin takes K22, so make it available
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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