175 lines
7.2 KiB
Python
Executable File
175 lines
7.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import kc705
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from liteeth.phy import LiteEthPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(150e6), with_ethernet=False, with_sata=False, **kwargs):
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platform = kc705.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on KC705",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT8JTF12864(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHY(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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clk_freq = self.clk_freq)
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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# SATA (Experimental) ----------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litex.soc.interconnect import wishbone
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from litesata.phy import LiteSATAPHY
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from litesata.core import LiteSATACore
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from litesata.frontend.arbitration import LiteSATACrossbar
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from litesata.frontend.dma import LiteSATABlock2MemDMA
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# IOs
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_sata_io = [
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# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
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("sfp", 0,
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Subsignal("txp", Pins("H2")),
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Subsignal("txn", Pins("H1")),
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Subsignal("rxp", Pins("G4")),
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Subsignal("rxn", Pins("G3")),
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),
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]
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platform.add_extension(_sata_io)
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# RefClk, Generate 150MHz from PLL.
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self.clock_domains.cd_sata_refclk = ClockDomain()
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self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
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sata_refclk = ClockSignal("sata_refclk")
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
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# PHY
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self.submodules.sata_phy = LiteSATAPHY(platform.device,
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refclk = sata_refclk,
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pads = platform.request("sfp"),
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gen = "gen1",
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clk_freq = sys_clk_freq,
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data_width = 16)
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# Core
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self.submodules.sata_core = LiteSATACore(self.sata_phy)
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# Crossbar
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self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
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# Block2Mem DMA
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bus = wishbone.Interface(data_width=32, adr_width=32)
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self.submodules.sata_block2mem = LiteSATABlock2MemDMA(
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user_port = self.sata_crossbar.get_port(),
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bus = bus,
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endianness = self.cpu.endianness)
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self.bus.add_master("sata_block2mem", master=bus)
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self.add_csr("sata_block2mem")
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# Timing constraints
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6)
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platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.sata_phy.crg.cd_sata_tx.clk,
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self.sata_phy.crg.cd_sata_tx.clk)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA)")
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args = parser.parse_args()
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soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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