199 lines
8.2 KiB
Python
199 lines
8.2 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# TimeCard project:
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# https://opencomputeproject.github.io/Time-Appliance-Project/docs/time-card/introduction
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# FPGA SoM:
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# http://www.alinx.vip:81/ug_en/AC7100B_User_Manual.pdf
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk125", 0,
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Subsignal("p", Pins("F6"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("E6"), IOStandard("DIFF_SSTL15"))
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),
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("clk200", 0,
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Subsignal("p", Pins("R4"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("T4"), IOStandard("DIFF_SSTL15"))
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),
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("rst_n", 0, Pins("T6"), IOStandard("LVCMOS15")),
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# Leds.
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("user_led", 0, Pins("B13"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("D14"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("D15"), IOStandard("LVCMOS33")),
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# Buttons.
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("user_btn", 0, Pins("J21"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("E13"), IOStandard("LVCMOS33")),
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# SPIFlash.
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("flash_cs_n", 0, Pins("T19"), IOStandard("LVCMOS33")),
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("flash", 0,
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("wp", Pins("P21")),
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Subsignal("hold", Pins("R21")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AA4 AB2 AA5 AB5 AB1 U3 W1 T1",
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"V2 U2 Y1 W2 Y2 U1 V3"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AA3 Y3 Y4"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("V4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("W4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AA1"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AB3"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("D2 G2 M2 M5"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"C2 G1 A1 F3 B2 F1 B1 E2",
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"H3 G3 H2 H5 J1 J5 K1 H4",
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"L4 M3 L3 J6 K3 K6 J4 L5",
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"P1 N4 R1 N2 M6 N5 P6 P2"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("E1 K2 M1 P5"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("D1 J2 L1 P4"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("T5"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("U5"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("W6"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("J20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("F10")),
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Subsignal("clk_n", Pins("E10")),
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Subsignal("rx_p", Pins("D11")),
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Subsignal("rx_n", Pins("C11")),
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Subsignal("tx_p", Pins("D5")),
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Subsignal("tx_n", Pins("C5")),
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),
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# Leds.
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("led", 0, Pins("E21"), IOStandard("LVCMOS33")),
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("led", 1, Pins("D21"), IOStandard("LVCMOS33")),
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("led", 2, Pins("E22"), IOStandard("LVCMOS33")),
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("led", 3, Pins("D22"), IOStandard("LVCMOS33")),
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# I2C.
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("i2c", 0,
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Subsignal("scl", Pins("N17"), Misc("PULLUP=True")),
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Subsignal("sda", Pins("T16"), Misc("PULLUP=True")),
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IOStandard("LVCMOS33")
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),
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# PMOD.
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("pmod", 0, Pins("M22 N22 H18 H17 H22 J22 K21 K22"), IOStandard("LVCMOS33")),
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# GPS.
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("gps", 0,
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Subsignal("rst_n", Pins("Y16")),
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Subsignal("tx", Pins("P20")),
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Subsignal("rx", Pins("N15")),
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Subsignal("tp", Pins("W14 Y14")),
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IOStandard("LVCMOS33")
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),
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("gps", 1,
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Subsignal("rst_n", Pins("G15")),
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Subsignal("tx", Pins("M17")),
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Subsignal("rx", Pins("J16")),
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Subsignal("tp", Pins("G17 G18")),
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IOStandard("LVCMOS33")
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),
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# SMAs.
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("sma", 0,
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Subsignal("dat_in", Pins("Y11"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
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Subsignal("dat_in_en", Pins("H15"), IOStandard("LVCMOS33")),
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Subsignal("dat_out", Pins("W11"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
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Subsignal("dat_out_en", Pins("J15"), IOStandard("LVCMOS33")),
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),
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("sma", 1,
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Subsignal("dat_in", Pins("Y12"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
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Subsignal("dat_in_en", Pins("J14"), IOStandard("LVCMOS33")),
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Subsignal("dat_out", Pins("W12"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
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Subsignal("dat_out_en", Pins("H14"), IOStandard("LVCMOS33")),
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),
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("sma", 2,
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Subsignal("dat_in", Pins("AA21"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
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Subsignal("dat_in_en", Pins("K14"), IOStandard("LVCMOS33")),
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Subsignal("dat_out", Pins("V10"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
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Subsignal("dat_out_en", Pins("K13"), IOStandard("LVCMOS33")),
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),
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("sma", 3,
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Subsignal("dat_in", Pins("AA20"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
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Subsignal("dat_in_en", Pins("L13"), IOStandard("LVCMOS33")),
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Subsignal("dat_out", Pins("W10"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
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Subsignal("dat_out_en", Pins("M13"), IOStandard("LVCMOS33")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self,toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7a100t-fgg484-2", _io, toolchain=toolchain)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
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"set_property CFGBVS VCCO [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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]
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self.toolchain.additional_commands = [
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# Non-Multiboot SPI-Flash bitstream generation.
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin",
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# Multiboot SPI-Flash Operational bitstream generation.
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"set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]",
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"write_bitstream -force {build_name}_operational.bit ",
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_operational.bit\" -file {build_name}_operational.bin",
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# Multiboot SPI-Flash Fallback bitstream generation.
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"set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]",
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"write_bitstream -force {build_name}_fallback.bit ",
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_fallback.bit\" -file {build_name}_fallback.bin"
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]
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def create_programmer(self, name='openocd'):
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if name == 'openocd':
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
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elif name == 'vivado':
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# TODO: some board versions may have s25fl128s
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return VivadoProgrammer(flash_part='s25fl256sxxxxxx0-spi-x1_x2_x4')
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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