183 lines
5.6 KiB
Python
183 lines
5.6 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("K21")),
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Subsignal("n", Pins("K22")),
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IOStandard("LVDS_25")
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),
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("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")),
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# Leds
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("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")),
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("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")),
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# Buttons
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("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")),
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("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")),
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("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")),
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("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")),
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# Serial
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("serial", 0,
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Subsignal("cts", Pins("F19")),
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Subsignal("rts", Pins("F18")),
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Subsignal("tx", Pins("B21")),
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Subsignal("rx", Pins("H17")),
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IOStandard("LVCMOS25")
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),
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# GMII Ethernet
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("eth_clocks", 0,
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# Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode
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Subsignal("gtx", Pins("AB7")),
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Subsignal("rx", Pins("P20")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("J22")),
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Subsignal("int_n", Pins("J20")),
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Subsignal("mdio", Pins("V20")),
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Subsignal("mdc", Pins("R19")),
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Subsignal("rx_dv", Pins("T22")),
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Subsignal("rx_er", Pins("U20")),
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Subsignal("rx_data", Pins("P19 Y22 Y21 W22 W20 V22 V21 U22")),
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Subsignal("tx_en", Pins("T8")),
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Subsignal("tx_er", Pins("U8")),
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Subsignal("tx_data", Pins("U10 T10 AB8 AA8 AB9 Y9 Y12 W12")),
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Subsignal("col", Pins("M16")),
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Subsignal("crs", Pins("N15")),
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IOStandard("LVCMOS25")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("LPC", {
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"DP0_C2M_P" : "B16",
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"DP0_C2M_N" : "A16",
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"DP0_M2C_P" : "D15",
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"DP0_M2C_N" : "C15",
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"LA06_P" : "D4",
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"LA06_N" : "D5",
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"LA10_P" : "H10",
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"LA10_N" : "H11",
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"LA14_P" : "C17",
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"LA14_N" : "A17",
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"LA18_CC_P" : "T12",
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"LA18_CC_N" : "U12",
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"LA27_P" : "AA10",
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"LA27_N" : "AB10",
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"IIC_SCL_MAIN" : "T21",
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"IIC_SDA_MAIN" : "R22",
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"CLK1_M2C_P" : "E16",
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"CLK1_M2C_N" : "F16",
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"LA00_CC_P" : "G9",
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"LA00_CC_N" : "F10",
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"LA03_P" : "B18",
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"LA03_N" : "A18",
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"LA08_P" : "B20",
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"LA08_N" : "A20",
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"LA12_P" : "H13",
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"LA12_N" : "G13",
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"LA16_P" : "C5",
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"LA16_N" : "A5",
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"GBTCLK0_M2C_P" : "E12",
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"GBTCLK0_M2C_N" : "F12",
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"LA01_CC_P" : "F14",
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"LA01_CC_N" : "F15",
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"LA05_P" : "C4",
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"LA05_N" : "A4",
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"LA09_P" : "F7",
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"LA09_N" : "F8",
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"LA13_P" : "G16",
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"LA13_N" : "F17",
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"LA17_CC_P" : "Y11",
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"LA17_CC_N" : "AB11",
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"LA23_P" : "U9",
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"LA23_N" : "V9",
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"LA26_P" : "U14",
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"LA26_N" : "U13",
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"PRSNT_M2C_L" : "Y16",
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"CLK0_M2C_P" : "H12",
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"CLK0_M2C_N" : "G11",
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"LA02_P" : "G8",
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"LA02_N" : "F9",
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"LA04_P" : "C19",
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"LA04_N" : "A19",
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"LA07_P" : "B2",
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"LA07_N" : "A2",
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"LA11_P" : "H14",
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"LA11_N" : "G15",
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"LA15_P" : "D18",
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"LA20_P" : "R9",
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"LA20_N" : "R8",
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"LA22_P" : "V7",
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"LA22_N" : "W8",
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"LA25_P" : "W14",
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"LA25_N" : "Y14",
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"LA29_P" : "T15",
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"LA29_N" : "U15",
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"LA31_P" : "U16",
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"LA31_N" : "V15",
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"LA33_P" : "Y17",
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"LA33_N" : "AB17",
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"LA32_N" : "Y18",
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"LA15_N" : "D19",
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"LA19_P" : "R11",
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"LA19_N" : "T11",
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"LA21_P" : "V11",
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"LA21_N" : "W11",
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"LA24_P" : "AA14",
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"LA24_N" : "AB14",
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"LA28_P" : "AA16",
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"LA28_N" : "AB16",
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"LA30_P" : "Y15",
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"LA30_N" : "AB15",
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"LA32_P" : "W17"
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}),
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("SMA_GPIO", {
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"P": "B3",
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"N": "A3"
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}),
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("SMA_USER_CLK", {
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"P": "M20",
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"N": "M19"
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}),
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("SMA_MGT_CLK", {
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"P": "C11",
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"N": "D11"
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}),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx45.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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