147 lines
6.0 KiB
Python
Executable File
147 lines
6.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Sylvain Munaut <tnt@246tNt.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# This target file provides a minimal LiteX SoC for the iCEBreaker-bitsy with a CPU,
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# its ROM (in SPI Flash), its SRAM, close to the others LiteX targets.
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# For more complete example of LiteX SoC for the iCEBreaker-bitsy with more features and
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# documentation can be found, refer to :
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# https://github.com/icebreaker-fpga/icebreaker-litex-examples
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import icebreaker_bitsy
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from litex.soc.cores.ram import Up5kSPRAM
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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# Clk/Rst
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clk12 = platform.request("clk12")
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rst_n = platform.request("user_btn_n")
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
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self.comb += pll.reset.eq(~rst_n) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), revision="v1", **kwargs):
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platform = icebreaker_bitsy.Platform(revision=revision)
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on iCEBreaker-bitsy",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=128*kB)
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self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
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self.bus.add_region("sram", SoCRegion(
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origin = self.bus.regions["psram"].origin + 0*kB,
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size = 64*kB,
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linker = True)
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)
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if not self.integrated_main_ram_size:
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self.bus.add_region("main_ram", SoCRegion(
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origin = self.bus.regions["psram"].origin + 64*kB,
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size = 64*kB,
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linker = True)
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)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--flash", action="store_true", help="Flash bitstream and bios")
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parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)")
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parser.add_argument("--bios-flash-offset", default=0xa0000, help="BIOS offset in SPI Flash (default: 0xa0000)")
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parser.add_argument("--revision", default="v1", help="Board revision 'v0' or 'v1'")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = args.bios_flash_offset,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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revision = args.revision,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.flash:
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from litex.build.dfu import DFUProg
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prog_gw = DFUProg(vid="1d50", pid="0x6146", alt=0)
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prog_sw = DFUProg(vid="1d50", pid="0x6146", alt=1)
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prog_gw.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"), reset=False)
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prog_sw.load_bitstream(os.path.join(builder.software_dir, 'bios/bios.bin'))
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if __name__ == "__main__":
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main()
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