153 lines
5.5 KiB
Python
153 lines
5.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Yu-Ti Kuo <bobgash2@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# embedfire rise pro FPGA: https://detail.tmall.com/item.htm?id=645153441975
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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from litex.build.xilinx.programmer import VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50" , 0, Pins("W19"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("N15"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("L21"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("K21"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("K22"), IOStandard("LVCMOS33")),
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# Buttons
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("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("W17"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("AA18"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("AB18"), IOStandard("LVCMOS33")),
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# Beeper (Buzzer)
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("beeper", 0, Pins("M17"), IOStandard("LVCMOS33")),
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# Fan
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("fan", 0, Pins("W22"), IOStandard("LVCMOS33")),
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# Serial CH340G
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("serial", 0,
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Subsignal("tx", Pins("N17")),
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Subsignal("rx", Pins("P17")),
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IOStandard("LVCMOS33")
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),
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# I2C EEPROM 24C64
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("i2c", 0,
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Subsignal("scl", Pins("E22")),
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Subsignal("sda", Pins("D22")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM MT41K256M16
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("ddram", 0,
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Subsignal("a", Pins(
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"AA4 AB2 AA5 AB3 AB1 U2 W1 R2",
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"V2 U3 Y1 W2 Y2 U1 V3"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("AA1 Y3 AA3"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("W6"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("U5"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("Y4"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("T1"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("D2 G2 M2 M5"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"C2 G1 A1 F3 B2 F1 B1 E2",
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"H3 G3 H2 H5 J1 J5 K1 H4",
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"L4 M3 L3 J6 K3 K6 J4 L5",
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"P1 N4 R1 N2 M6 N5 P6 P2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("E1 K2 M1 P5"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("D1 J2 L1 P4"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("V4"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("W4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("AB5"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("T5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("R3"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet (RTL8211F)
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("eth_clocks", 0,
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Subsignal("tx", Pins("C18")),
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Subsignal("rx", Pins("C19")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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#SubSignal("inib"), Pins("D21")),
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#Subsignal("rst_n", Pins("E21")),
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Subsignal("mdio", Pins("G22")),
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Subsignal("mdc", Pins("G21")),
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Subsignal("rx_ctl", Pins("C22")),
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Subsignal("rx_data", Pins("D20 C20 A18 A19")),
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Subsignal("tx_ctl", Pins("B22")),
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Subsignal("tx_data", Pins("B20 A20 B21 A21")),
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IOStandard("LVCMOS33")
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("cd", Pins("AA19")),
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Subsignal("clk", Pins("Y22")),
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Subsignal("mosi", Pins("Y21")),
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Subsignal("cs_n", Pins("A14")),
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Subsignal("miso", Pins("AB21")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("AB21 AB22 AB20 W21"),),
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Subsignal("cmd", Pins("Y21"),),
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Subsignal("clk", Pins("Y22")),
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Subsignal("cd", Pins("AA19")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [] # ToDo
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, variant="a7-35", toolchain="vivado"):
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device = {
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"a7-35": "xc7a35tfgg484-2",
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"a7-100": "xc7a100tfgg484-2",
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"a7-200": "xc7a200tfbg484-2"
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}[variant]
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer(flash_part="mt25ql128-spi-x1_x2_x4")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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