225 lines
9.7 KiB
Python
Executable File
225 lines
9.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import re
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import alibaba_vu13p
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT40A512M16
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from litedram.phy import usddrphy
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from liteeth.phy.usp_gty_1000basex import USP_GTY_1000BASEX
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from litepcie.phy.usppciephy import USPPCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, ddram_channel=0):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_pll4x = ClockDomain()
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self.cd_eth = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk400", 0), 400e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_eth, 200e6, margin=0)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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]
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ddr_pad = platform.request("ddram_refclk", ddram_channel)
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self.specials += [Instance("IBUFDS",
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i_I = ddr_pad.p,
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i_IB = ddr_pad.n,
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o_O = self.cd_idelay.clk,
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)]
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self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=125e6,
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ddram_channel = 0,
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with_led_chaser = True,
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with_ethernet = False,
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with_etherbone = False,
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ethernet_port = "qsfp0_sfp0",
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etherbone_port = "qsfp0_sfp0",
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ethernet_ip = "192.168.1.50",
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eth_dynamic_ip = True,
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remote_ip = None,
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etherbone_ip = "192.168.1.50",
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with_pcie = False,
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**kwargs):
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platform = alibaba_vu13p.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, ddram_channel)
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kwargs["uart_name"] = "crossover"
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kwargs["with_jtagbone"] = True
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alibaba VU13P", **kwargs)
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# Running LED
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self.comb += platform.request("run_led").eq(~ResetSignal("sys"))
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 400e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT40A512M16(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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def parse_qsfp_port(port_string):
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match = re.match(r"qsfp(\d+)_sfp(\d+)", port_string)
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qsfp_id = int(match.group(1))
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sfp_lane = int(match.group(2))
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return (qsfp_id, sfp_lane)
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qsfp_in_use = [False, False]
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if with_ethernet:
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qsfp_id, sfp_lane = parse_qsfp_port(ethernet_port)
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self.ethphy = USP_GTY_1000BASEX(self.crg.cd_eth.clk,
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data_pads = self.platform.request("qsfp{}_sfp".format(qsfp_id), sfp_lane),
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sys_clk_freq = self.clk_freq,
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refclk_from_fabric = True)
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self.add_ethernet(phy=self.ethphy, local_ip=ethernet_ip if not eth_dynamic_ip else None, dynamic_ip=eth_dynamic_ip, remote_ip=remote_ip)
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qsfp_in_use[qsfp_id] = True
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if with_etherbone:
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qsfp_id, sfp_lane = parse_qsfp_port(etherbone_port)
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self.bonephy = USP_GTY_1000BASEX(self.crg.cd_eth.clk,
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data_pads = self.platform.request("qsfp{}_sfp".format(qsfp_id), sfp_lane),
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sys_clk_freq = self.clk_freq,
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refclk_from_fabric = True)
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self.add_etherbone(phy=self.bonephy, ip_address=etherbone_ip)
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qsfp_in_use[qsfp_id] = True
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for qsfp_id, in_use in enumerate(qsfp_in_use):
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if in_use:
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resetl = platform.request("qsfp_resetl", qsfp_id)
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lpmode = platform.request("qsfp_lpmode", qsfp_id)
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reset_cycles = int(sys_clk_freq * 10e-3) # 1ms as tested with multiple SFP modules
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reset_count = Signal(max=reset_cycles+1, reset=reset_cycles)
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self.sync += [
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If(ResetSignal("sys"),
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reset_count.eq(reset_cycles)
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).Elif(reset_count != 0,
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reset_count.eq(reset_count - 1)
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)
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]
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self.comb += resetl.eq(~(ResetSignal("sys") | (reset_count != 0)))
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self.comb += lpmode.eq(0)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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sfp_list = []
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for qsfp in range(2):
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for sfp in range(4):
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sfp_list.append("qsfp{}_{}".format(qsfp, sfp))
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parser = LiteXArgumentParser(platform=alibaba_vu13p.Platform, description="LiteX SoC on Alibaba VU13P.")
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parser.add_target_argument("--flash", action="store_true", help="Write FPGA bitstream into spi flash.")
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parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--ddram-channel", default=0, type=int, choices=range(4), help="DDRAM channel.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--ethernet-port", default="qsfp0_sfp0", choices=sfp_list, help="Ethernet SFP port.")
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parser.add_target_argument("--etherbone-port", default="qsfp0_sfp0", choices=sfp_list, help="Etherbone SFP port.")
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parser.add_target_argument("--ethernet-ip", default="192.168.1.50", help="Ethernet IP address.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--etherbone-ip", default="192.168.1.50", help="Ethernet IP address.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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args = parser.parse_args()
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if args.with_ethernet and args.with_etherbone:
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if args.ethernet_port == args.etherbone_port:
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parser.error("Ethernet and Etherbone SFP ports must be different.")
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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ddram_channel = args.ddram_channel,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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ethernet_port = args.ethernet_port,
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etherbone_port = args.etherbone_port,
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ethernet_ip = args.ethernet_ip,
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remote_ip = args.remote_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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etherbone_ip = args.etherbone_ip,
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with_pcie = args.with_pcie,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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