183 lines
8.2 KiB
Python
Executable File
183 lines
8.2 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.gen.genlib.misc import WaitTimer
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from litex_boards.platforms import efinix_titanium_ti60_f225_dev_kit
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.hyperbus import HyperRAM
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from liteeth.phy.titaniumrgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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self.cd_rst = ClockDomain(reset_less=True)
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# # #
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clk25 = platform.request("clk25")
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rst_n = platform.request("user_btn", 0)
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self.comb += self.cd_rst.clk.eq(clk25)
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# A pulse is necessary to do a reset.
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self.rst_pulse = Signal()
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self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq))
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self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done)
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self.comb += reset_timer.wait.eq(self.rst)
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# PLL
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self.pll = pll = TITANIUMPLL(platform)
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self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
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pll.register_clkin(clk25, platform.default_clk_freq)
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# You can use CLKOUT0 only for clocks with a maximum frequency of 4x
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# (integer) of the reference clock. If all your system clocks do not fall within
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# this range, you should dedicate one unused clock for CLKOUT0.
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pll.create_clkout(None, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=0, with_reset=True)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq, phase=0, with_reset=True)
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pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=315, with_reset=True)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=200e6,
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with_spi_flash = False,
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with_hyperram = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_phy = 0,
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eth_ip = "192.168.1.50",
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remote_ip = None,
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**kwargs):
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platform = efinix_titanium_ti60_f225_dev_kit.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q64JW
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q64JW(Codes.READ_1_1_1), with_master=True)
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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# HyperRAM Parameters.
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hyperram_device = "W958D6NW"
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hyperram_size = 32 * MEGABYTE
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hyperram_cache_size = 16 * KILOBYTE
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# HyperRAM Bus/Slave Interface.
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hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size, mode="rwx"))
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# HyperRAM L2 Cache.
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hyperram_cache = wishbone.Cache(
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cachesize = hyperram_cache_size//4,
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master = hyperram_bus,
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slave = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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)
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hyperram_cache = FullMemoryWE()(hyperram_cache)
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self.hyperram_cache = hyperram_cache
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self.add_config("L2_SIZE", hyperram_cache_size)
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# HyperRAM Core.
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self.hyperram = HyperRAM(
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pads = platform.request("hyperram"),
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latency = 7,
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latency_mode = "variable",
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sys_clk_freq = sys_clk_freq,
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clk_ratio = "2:1",
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dq_i_cd = "sys2x_ps",
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)
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self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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platform.add_extension(efinix_titanium_ti60_f225_dev_kit.rgmii_ethernet_qse_ios("P1"))
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pads = platform.request("eth", eth_phy)
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self.ethphy = LiteEthPHYRGMII(
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platform = platform,
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clock_pads = platform.request("eth_clocks", eth_phy),
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pads = pads,
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with_hw_init_reset = False)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, local_ip=eth_ip, remote_ip=remote_ip, software_debug=False)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=efinix_titanium_ti60_f225_dev_kit.Platform, description="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=200e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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parser.add_target_argument("--with-hyperram", action="store_true", help="Enable HyperRAM.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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with_hyperram = args.with_hyperram,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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remote_ip = args.remote_ip,
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eth_phy = args.eth_phy,
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**parser.soc_argdict)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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from litex.build.openfpgaloader import OpenFPGALoader
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prog = OpenFPGALoader("titanium_ti60_f225")
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
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if __name__ == "__main__":
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main()
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