203 lines
9.5 KiB
Python
Executable File
203 lines
9.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import math
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import json
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from migen import *
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from litex_boards.platforms import datacenter_ddr4_test_board
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy.s7ddrphy import A7DDRPHY
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from litedram.init import get_sdram_phy_py_header
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from litedram.core.controller import ControllerSettings
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from litedram.common import PhySettings, GeomSettings, TimingSettings
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from liteeth.phy import LiteEthS7PHYRGMII
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from litex.soc.cores.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
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with_led_chaser=True, eth_reset_time, **kwargs):
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platform = datacenter_ddr4_test_board.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on data center test board",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq)
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# DDR4 SDRAM RDIMM -------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = A7DDRPHY(platform.request("ddr4"),
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memtype = "DDR4",
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iodelay_clk_freq = iodelay_clk_freq,
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sys_clk_freq = sys_clk_freq,
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is_rdimm = True,
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = 256,
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size = 0x40000000,
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)
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
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# SD Card ----------------------------------------------------------------------------------
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if with_sdcard:
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self.add_sdcard()
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
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# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
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# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
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self.submodules.ethphy = LiteEthS7PHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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rx_delay = 0.8e-9,
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hw_reset_cycles = math.ceil(float(eth_reset_time) * self.sys_clk_freq)
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)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# UartBone ---------------------------------------------------------------------------------
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if with_uartbone:
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self.add_uartbone("serial", baudrate=1e6)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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def generate_sdram_phy_py_header(self, output_file):
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os.makedirs(os.path.dirname(output_file), exist_ok=True)
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f = open(output_file, "w")
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f.write(get_sdram_phy_py_header(
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self.sdram.controller.settings.phy,
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self.sdram.controller.settings.timing))
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f.close()
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# Build --------------------------------------------------------------------------------------------
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class LiteDRAMSettingsEncoder(json.JSONEncoder):
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def default(self, o):
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if isinstance(o, (ControllerSettings, GeomSettings, PhySettings, TimingSettings)):
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ignored = ['self', 'refresh_cls']
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return {k: v for k, v in vars(o).items() if k not in ignored}
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elif isinstance(o, Signal) and isinstance(o.reset, Constant):
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return o.reset
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elif isinstance(o, Constant):
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return o.value
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print('o', end=' = '); __import__('pprint').pprint(o)
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return super().default(o)
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on LPDDR4 Test Board")
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target = parser.add_argument_group(title="Target options")
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target.add_argument("--build", action="store_true", help="Build bitstream.")
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target.add_argument("--load", action="store_true", help="Load bitstream.")
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target.add_argument("--flash", action="store_true", help="Flash bitstream.")
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target.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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target.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency.")
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ethopts = target.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
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target.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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target.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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target.add_argument("--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset")
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target.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
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target.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
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target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
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target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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iodelay_clk_freq = int(float(args.iodelay_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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eth_reset_time = args.eth_reset_time,
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with_hyperram = args.with_hyperram,
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with_sdcard = args.with_sdcard,
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with_jtagbone = args.with_jtagbone,
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with_uartbone = args.with_uartbone,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build(**vivado_build_argdict(args), run=args.build)
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builder.soc.generate_sdram_phy_py_header(os.path.join(builder.output_dir, "sdram_init.py"))
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# LiteDRAM settings (controller, phy, geom, timing)
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with open(os.path.join(builder.output_dir, 'litedram_settings.json'), 'w') as f:
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json.dump(builder.soc.sdram.controller.settings, f, cls=LiteDRAMSettingsEncoder, indent=4)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
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if __name__ == "__main__":
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main()
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