166 lines
6.8 KiB
Python
Executable File
166 lines
6.8 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# python3 -m litex_boards.targets.sqrl_fk33 --with-hbm --sys-clk-freq=250e6 --csr-csv=csr.csv --build --load
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# litex_server --jtag --jtag-config=openocd_xc7_ft2232.cfg --jtag-chain=2
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# litex_term crossover
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import os
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import sqrl_fk33
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.interconnect.axi import *
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from litex.soc.cores.ram.xilinx_usp_hbm2 import USPHBM2
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from litex.soc.cores.led import LedChaser
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from litepcie.phy.usppciephy import USPHBMPCIEPHY
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from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_hbm):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if with_hbm:
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self.cd_hbm_ref = ClockDomain()
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self.cd_apb = ClockDomain()
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# # #
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self.pll = pll = USPMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_hbm:
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pll.create_clkout(self.cd_hbm_ref, 100e6)
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pll.create_clkout(self.cd_apb, 100e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, with_hbm=False, **kwargs):
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platform = sqrl_fk33.Platform()
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if with_hbm:
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assert 225e6 <= sys_clk_freq <= 450e6
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_hbm)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("uart_name", "serial") == "serial":
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kwargs["uart_name"] = "crossover" # Defaults to Crossover-UART.
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on FK33", **kwargs)
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# JTAGBone --------------------------------------------------------------------------------
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self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
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# HBM --------------------------------------------------------------------------------------
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if with_hbm:
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# Add HBM Core.
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self.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(USPHBM2(platform))
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# Get HBM .xci.
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os.system("wget https://github.com/litex-hub/litex-boards/files/8178874/hbm_0.xci.txt")
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os.makedirs("ip/hbm", exist_ok=True)
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os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
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# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
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for i in range(4):
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axi_hbm = hbm.axi[i]
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axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33)
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self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
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self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB.
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# Link HBM2 channel 0 as main RAM
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self.bus.add_region("main_ram", SoCRegion(origin=0x4000_0000, size=0x1000_0000, linker=True)) # 256MB.
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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assert self.csr_data_width == 32
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# PHY
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self.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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# Endpoint
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self.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
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# Wishbone bridge
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self.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.bus.add_master(master=self.pcie_bridge.wishbone)
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# DMA0
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self.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_constant("DMA_CHANNELS", 1)
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# MSI
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self.pcie_msi = LitePCIeMSI()
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sqrl_fk33.Platform, description="LiteX SoC on FK33")
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parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--with-hbm", action="store_true", help="Use HBM2.")
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parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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with_hbm = args.with_hbm,
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**parser.soc_core_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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