126 lines
5.1 KiB
Python
Executable File
126 lines
5.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import deca
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from litex.soc.cores.clock import Max10PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_usb = ClockDomain()
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# # #
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# Clk / Rst.
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 40e6)
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# USB PLL.
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if with_usb_pll:
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ulpi = platform.request("ulpi")
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self.comb += ulpi.cs.eq(1) # Enable ULPI chip to enable the ULPI clock.
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self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(ulpi.clk, 60e6)
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pll.create_clkout(self.cd_usb, 60e6, phase=-120) # -120° from DECA's example (also validated with LUNA).
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_uartbone=False, with_jtagbone=False,
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with_video_terminal=False,
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**kwargs):
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self.platform = platform = deca.Platform()
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# Defaults to JTAG-UART since no hardware UART.
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real_uart_name = kwargs["uart_name"]
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if real_uart_name == "serial":
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if with_jtagbone:
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kwargs["uart_name"] = "crossover"
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else:
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kwargs["uart_name"] = "jtag_atlantic"
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if with_uartbone:
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kwargs["uart_name"] = "crossover"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Terasic DECA",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
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# UARTbone ---------------------------------------------------------------------------------
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if with_uartbone:
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self.add_uartbone(name=real_uart_name, baudrate=kwargs["uart_baudrate"])
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# JTAGbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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parser.add_argument("--with-uartbone", action="store_true", help="Enable UARTbone support.")
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parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_uartbone = args.with_uartbone,
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with_jtagbone = args.with_jtagbone,
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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