202 lines
6.9 KiB
Python
202 lines
6.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Greg Davill <greg.davill@gmail.com>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io_r1_0 = [
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# Clk
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("clk30", 0, Pins("B12"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("C13"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D12"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins(" U2"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins(" T3"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("D13"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("E13"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("C16"), IOStandard("LVCMOS33")),
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("user_led_color", 0, Pins("T1 R1 U1"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("U16"), IOStandard("SSTL135_I")),
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("user_btn", 1, Pins("T17"), IOStandard("SSTL135_I")),
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# SPIFlash
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("R2")),
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#Subsignal("clk", Pins("U3")),
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Subsignal("dq", Pins("W2 V2 Y2 W1")),
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IOStandard("LVCMOS33")
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins(f"B15")),
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Subsignal("mosi", Pins(f"A13"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins(f"A14"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins(f"C12"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("C12 A12 D14 A14"), Misc("PULLMODE=UP")),
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Subsignal("cmd", Pins("A13"), Misc("PULLMODE=UP")),
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Subsignal("clk", Pins("B13")),
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Subsignal("cd", Pins("B15"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"G16 E19 E20 F16 F19 E16 F17 L20 "
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"M20 E18 G18 D18 H18 C18 D17 G20 "),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("H16 F20 H20"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("K18"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("J17"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("G19"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("J20 J16"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("U20 L18"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"U19 T18 U18 R20 P18 P19 P20 N20",
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"L19 L17 L16 R16 N18 R17 N17 P17"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("T19 N16"), IOStandard("SSTL135D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("C20 J19"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("F18 J18"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("K20 H17"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("E17"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST")
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),
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("vccio_ctrl", 0,
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Subsignal("pdm", Pins("V1 E11 T2")),
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Subsignal("en", Pins("E12"))
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("E15")),
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Subsignal("rx", Pins("D11")),
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("B20")),
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Subsignal("mdio", Pins("D16")),
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Subsignal("mdc", Pins("A19")),
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Subsignal("rx_data", Pins("A16 C17 B17 A17")),
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Subsignal("tx_ctl", Pins("D15")),
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Subsignal("rx_ctl", Pins("B18")),
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Subsignal("tx_data", Pins("C15 B16 A18 B19")),
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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("ulpi", 0,
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Subsignal("data", Pins("B9 C6 A7 E9 A8 D9 C10 C7")),
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Subsignal("clk", Pins("B6")),
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Subsignal("dir", Pins("A6")),
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Subsignal("nxt", Pins("B8")),
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Subsignal("stp", Pins("C8")),
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Subsignal("rst", Pins("C9")),
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IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_r1_0 = [
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("SYZYGY0", {
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# single ended
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"S0": "G2", "S1": "J3",
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"S2": "F1", "S3": "K3",
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"S4": "J4", "S5": "K2",
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"S6": "J5", "S7": "J1",
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"S8": "N2", "S9": "L3",
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"S10":"M1", "S11":"L2",
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"S12":"N3", "S13":"N4",
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"S14":"M3", "S15":"P5",
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"S16":"H1", "S17":"K5",
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"S18":"K4", "S19":"K1",
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"S20":"L4", "S21":"L1",
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"S22":"L5", "S23":"M4",
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"S24":"N1", "S25":"N5",
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"S26":"P3", "S27":"P4",
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"S28":"H2", "S29":"P1",
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"S30":"G1", "S31":"P2",
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}
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),
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("SYZYGY1", {
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# single ended
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"S0": "E4", "S1": "A4",
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"S2": "D5", "S3": "A5",
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"S4": "C4", "S5": "B2",
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"S6": "B4", "S7": "C2",
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"S8": "A2", "S9": "C1",
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"S10":"B1", "S11":"D1",
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"S12":"F4", "S13":"D2",
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"S14":"E3", "S15":"E1",
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"S16":"B5", "S17":"E5",
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"S18":"F5", "S19":"C5",
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"S20":"B3", "S21":"A3",
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"S22":"D3", "S23":"C3",
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"S24":"H5", "S25":"G5",
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"S26":"H3", "S27":"H4",
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"S28":"G3", "S29":"F2",
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"S30":"F3", "S31":"E2",
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}
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),
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("SYZYGY2", {
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# single ended
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"S0": "C11", "S1": "B11",
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"S2": "D6", "S3": "D7",
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"S4": "E6", "S5": "E7",
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"S6": "D8", "S7": "E8",
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"S8": "E10", "S9": "D10",
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"S10":"A9", "S11":"A10",
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"S12":"B10", "S13":"A11"
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}
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),
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]
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# SYZYGY -------------------------------------------------------------------------------------------
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def raw_syzygy_io(syzygy, iostandard="LVCMOS33"):
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return [(syzygy, 0, Pins(" ".join([f"{syzygy}:S{i:d}" for i in range(32)])), IOStandard(iostandard))]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk30"
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default_clk_period = 1e9/30e6
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def __init__(self, revision="1.0", device="85F", toolchain="trellis", **kwargs):
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assert revision in ["1.0"]
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self.revision = revision
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io = {"1.0": _io_r1_0}[revision]
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connectors = {"1.0": _connectors_r1_0}[revision]
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LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_butterstick.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk30", loose=True), 1e9/30e6)
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