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9e5224ca49
Along the way I added UARTbone support to DECA as well for debugging. Examples: ./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg litex_term crossover ./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
22 lines
723 B
INI
22 lines
723 B
INI
source [find interface/altera-usb-blaster2.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME 10m50
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}
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# user-defined chains are 0xC (12) or 0xE (14)
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# they are the same, single, scan-chain disgtinguished by the usr1user bit
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jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
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-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
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-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
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-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
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-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
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# unneeded
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# suppresses warning
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gdb_port disabled
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tcl_port disabled
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telnet_port disabled
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