121 lines
4.5 KiB
Python
121 lines
4.5 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Felix Domke <tmbinc@elitedvb.net>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [ # Documented by https://github.com/360nosc0pe project.
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# Leds
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("user_led", 0, Pins("G16"), IOStandard("LVCMOS33")),
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# Beeper
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("beeper", 0, Pins("W17"), IOStandard("LVCMOS33")),
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# Led Frontpanel
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("led_frontpanel", 0,
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Subsignal("cs_n", Pins("N22")), # CLK
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Subsignal("clk", Pins("R20")), # SCLK
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Subsignal("mosi", Pins("P22")), # SERDATA
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Subsignal("oe", Pins("R21")), # OE
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IOStandard("LVCMOS15"),
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),
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# Button Frontpanel
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("btn_frontpanel", 0,
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Subsignal("clk", Pins("H18")),
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Subsignal("cs_n", Pins("G19")),
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Subsignal("miso", Pins("G17")),
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IOStandard("LVCMOS33")
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),
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# LCD
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("lcd", 0,
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Subsignal("clk", Pins("D20")),
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Subsignal("vsync", Pins("A21")),
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Subsignal("hsync", Pins("A22")),
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Subsignal("r", Pins("G22 F22 F21 F19 F18 F17")),
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Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")),
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Subsignal("b", Pins("D22 D21 C22 C20 B22 B21")),
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IOStandard("LVCMOS33"),
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),
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# MII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("B19")),
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Subsignal("rx", Pins("C17")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R6"), IOStandard("LVCMOS25")),
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Subsignal("mdio", Pins("E15")),
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Subsignal("mdc", Pins("D15")),
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Subsignal("rx_dv", Pins("A16")),
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Subsignal("rx_er", Pins("C15")),
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Subsignal("rx_data", Pins("D16 A17 B17 D17")),
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Subsignal("tx_en", Pins("A18")),
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Subsignal("tx_data", Pins("C18 A19 C19 B20")),
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Subsignal("col", Pins("B16")),
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Subsignal("crs", Pins("B15")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"J21 K18 J18 R16 P16 T18 R18 T19",
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"R19 P18 P17 P15 N15"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("K21 J20 J22"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("L21"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("L22"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("K19"), IOStandard("SSTL15")),
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#Subsignal("cs_n", Pins(""), IOStandard("SSTL15")), # Pulled low.
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#Subsignal("dm", Pins(""), IOStandard("SSTL15")), # Pulled low.
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Subsignal("dq", Pins(
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" T21 U21 T22 U22 W20 W21 U20 V20",
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"AA22 AB22 AA21 AB21 AB19 AB20 Y19 AA19",
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" W16 Y16 U17 V17 AA17 AB17 AA16 AB16",
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" V14 V13 W13 Y14 AA14 Y13 AA13 AB14"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("V22 Y20 U15 W15"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("W22 Y21 U16 Y15"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("T16"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("T17"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("M21"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("M22"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("V18"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain="vivado")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/25e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/25e6)
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