180 lines
7.9 KiB
Python
Executable File
180 lines
7.9 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# ./terasic_deca.py --uart-name jtag_uart --build --load
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# litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
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from migen import *
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from litex_boards.platforms import terasic_deca
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from litex.gen import *
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from litex.soc.cores.clock import Max10PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.led import LedChaser
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_hdmi = ClockDomain()
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self.cd_usb = ClockDomain()
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# # #
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# Clk / Rst.
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clk50 = platform.request("clk50")
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# PLL
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self.pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 40e6)
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# USB PLL.
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if with_usb_pll:
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ulpi = platform.request("ulpi")
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self.comb += ulpi.cs.eq(1) # Enable ULPI chip to enable the ULPI clock.
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self.usb_pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(ulpi.clk, 60e6)
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pll.create_clkout(self.cd_usb, 60e6, phase=-120) # -120° from DECA's example (also validated with LUNA).
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=50e6,
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with_led_chaser = True,
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with_uartbone = False,
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with_jtagbone = False,
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with_video_terminal = False,
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with_spi_sdcard = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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eth_dynamic_ip = False,
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**kwargs):
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self.platform = platform = terasic_deca.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
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# SoCCore ----------------------------------------------------------------------------------
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# Defaults to JTAG-UART since no hardware UART.
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real_uart_name = kwargs["uart_name"]
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if real_uart_name == "serial":
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if with_jtagbone:
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kwargs["uart_name"] = "crossover"
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else:
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kwargs["uart_name"] = "jtag_uart"
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if with_uartbone:
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Terasic DECA", **kwargs)
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# UARTbone ---------------------------------------------------------------------------------
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if with_uartbone:
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self.add_uartbone(uart_name=real_uart_name, baudrate=kwargs["uart_baudrate"])
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# JTAGbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.platform.toolchain.additional_sdc_commands += [
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'create_clock -name eth_rx_clk -period 40.0 [get_ports {eth_clocks_rx}]',
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'create_clock -name eth_tx_clk -period 40.0 [get_ports {eth_clocks_tx}]',
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'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_rx_clk}]',
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'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_tx_clk}]',
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'set_false_path -from [get_clocks {eth_rx_clk}] -to [get_clocks {eth_tx_clk}]',
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]
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self.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# SPI SD card ------------------------------------------------------------------------------
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if with_spi_sdcard:
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self.add_spi_sdcard()
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sd_aux = self.platform.request("spisdcard_aux")
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# Set the SD card supply to 3.3V
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self.comb += sd_aux.sel.eq(0)
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# Set the direction of the level shifter (0 = SD to FPGA; 1 = FPGA to SD)
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self.comb += sd_aux.cmd_dir.eq(1)
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self.comb += sd_aux.d0_dir.eq(0)
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self.comb += sd_aux.d123_dir.eq(1)
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# Keep the unused data lines high
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self.comb += sd_aux.dat1.eq(1)
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self.comb += sd_aux.dat2.eq(1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=terasic_deca.Platform, description="LiteX SoC on DECA.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--with-uartbone", action="store_true", help="Enable UARTbone support.")
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parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI SD card controller.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_uartbone = args.with_uartbone,
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with_jtagbone = args.with_jtagbone,
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with_video_terminal = args.with_video_terminal,
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with_spi_sdcard = args.with_spi_sdcard,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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