103 lines
3.6 KiB
Python
103 lines
3.6 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Ilia Sergachev <ilia.sergachev@protonmail.ch>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("L19"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("B20"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("A19"), IOStandard("LVCMOS33")),
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),
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# Buttons
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("user_btn", 0, Pins("M19"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("M20"), IOStandard("LVCMOS33")),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("M1")),
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Subsignal("rx", Pins("H2")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("int_n", Pins("F1")),
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Subsignal("rst_n", Pins("J3")),
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Subsignal("mdio", Pins("G2")),
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Subsignal("mdc", Pins("G1")),
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Subsignal("rx_ctl", Pins("H1")),
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Subsignal("rx_data", Pins("J1 K2 K1 L2"), Misc("PULLMODE=UP")), # RGMII mode - Advertise all capabilities.
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Subsignal("tx_ctl", Pins("L1")),
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Subsignal("tx_data", Pins("P1 P2 N1 N2")),
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IOStandard("LVCMOS25")
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins("P19")),
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Subsignal("cs_n", Pins("U19"), Misc("PULLMODE=UP")),
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Subsignal("mosi", Pins("T20"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins("N20"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("clk", Pins("P19")),
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Subsignal("cd", Pins("T18"), Misc("PULLMODE=UP")),
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Subsignal("cmd", Pins("T20"), Misc("PULLMODE=UP")),
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Subsignal("data", Pins("N20 N19 U20 U19"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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# HDMI
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("hdmi_i2c", 0,
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Subsignal("scl", Pins("C9")),
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Subsignal("sda", Pins("C8")),
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IOStandard("LVCMOS33")
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),
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("hdmi", 0,
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Subsignal("clk_p", Pins("C4"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data0_p", Pins("A4"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data1_p", Pins("A2"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")), # P/N Swap on PCB, invert in logic.
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Subsignal("data2_p", Pins("C1"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")), # P/N Swap on PCB, invert in logic.
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod1", "B6 A7 A8 A9 A6 B8 B9 A10"),
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("pmod2", "A11 A12 A13 A14 B10 B11 B12 B13"),
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("pmod3", "B15 B16 B17 B18 A15 A16 A17 A18"),
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("pmod4", "D19 E19 F19 G19 C20 D20 E20 F20"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/506
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def __init__(self, toolchain="trellis", **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381I", _io, _connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenFPGALoader("ecpix5")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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