93 lines
3.1 KiB
Python
Executable File
93 lines
3.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 John Simons <jammsimons@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import arduino_mkrvidor4000
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from litex.soc.cores.clock import Cyclone10LPPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litedram.modules import AS4C4M16
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk48 = platform.request("clk48")
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# PLL
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self.pll = pll = Cyclone10LPPLL(speedgrade="-C8")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=48e6, **kwargs):
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platform = arduino_mkrvidor4000.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MKR Vidor 4000", **kwargs)
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self.add_jtagbone() # TODO: untested
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = AS4C4M16(sys_clk_freq, "1:1"), # Alliance Memory AS4C4M16
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=arduino_mkrvidor4000.Platform, description="LiteX SoC on MKR Vidor 4000.")
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parser.add_argument("--sys-clk-freq", default=48e6, type=float, help="System clock frequency.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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