214 lines
9.3 KiB
Python
Executable File
214 lines
9.3 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Note: For now with --toolchain=yosys+nextpnr:
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# - DDR3 should be disabled: ex --integrated-main-ram-size=8192
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# - Clk Freq should be lowered: ex --sys-clk-freq=50e6
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import digilent_arty
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn, GPIOTristate
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.dna import DNA
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_eth = ClockDomain()
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if with_dram:
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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eth_dynamic_ip = False,
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with_led_chaser = True,
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with_jtagbone = True,
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with_spi_flash = False,
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with_buttons = False,
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with_pmod_gpio = False,
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**kwargs):
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platform = digilent_arty.Platform(variant=variant, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
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self.crg = _CRG(platform, sys_clk_freq, with_dram)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs)
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# XADC -------------------------------------------------------------------------------------
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self.xadc = XADC()
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# DNA --------------------------------------------------------------------------------------
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import S25FL128L
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate="1:2", with_master=True)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq,
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)
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(
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pads = platform.request_all("user_btn"),
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with_irq = self.irq.enabled
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)
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# GPIOs ------------------------------------------------------------------------------------
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if with_pmod_gpio:
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platform.add_extension(digilent_arty.raw_pmod_io("pmoda"))
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self.gpio = GPIOTristate(
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pads = platform.request("pmoda"),
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with_irq = self.irq.enabled
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=digilent_arty.Platform, description="LiteX SoC on Arty A7.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_target_argument("--sdcard-adapter", help="SDCard PMOD adapter (digilent or numato).")
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parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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parser.add_target_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_jtagbone = args.with_jtagbone,
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with_spi_flash = args.with_spi_flash,
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with_pmod_gpio = args.with_pmod_gpio,
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**parser.soc_argdict
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)
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if args.sdcard_adapter == "numato":
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soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io)
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else:
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soc.platform.add_extension(digilent_arty._sdcard_pmod_io)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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