159 lines
6.0 KiB
Python
Executable File
159 lines
6.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# ./limesdr_mini_v2.py --csr-csv=csr.csv --build --load
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# litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
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# litex_term crossover
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from migen import *
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from litex.gen import LiteXModule
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from litex_boards.platforms import limesdr_mini_v2
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import stream
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.cores.usb_fifo import FT245PHYSynchronous
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from litescope import LiteScopeAnalyzer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_usb = ClockDomain()
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# # #
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# Clk.
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clk40 = platform.request("clk40")
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# PLL.
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk40, 40e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# USB.
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self.comb += self.cd_usb.clk.eq(platform.request("usb_fifo_clk"))
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# BoardInfo ----------------------------------------------------------------------------------------
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class BoardInfo(LiteXModule, AutoCSR):
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def __init__(self, revision_pads):
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self.revision = CSRStorage(fields=[
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CSRField("hardware", size=4, description="Hardware Revision."),
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CSRField("bom", size=4, description="Bill of Material Revision."),
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])
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# # #
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self.comb += self.revision.fields.hardware.eq(revision_pads.hardware)
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self.comb += self.revision.fields.bom .eq(revision_pads.bom)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=80e6, toolchain="trellis",
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with_usb_fifo = True, with_usb_fifo_loopback=False,
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with_led_chaser = True,
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**kwargs):
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platform = limesdr_mini_v2.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LimeSDR-Mini-V2", **kwargs)
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# JTAGBone ---------------------------------------------------------------------------------
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self.add_jtagbone()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# Info -------------------------------------------------------------------------------------
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self.info = BoardInfo(platform.request("revision"))
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# I2C Bus ----------------------------------------------------------------------------------
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# - Temperature Sensor (LM72 @ 0x48).
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# - Eeprom (M24128 @ 0x50) / Not populated.
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self.i2c = I2CMaster(platform.request("i2c"))
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# USB-FIFO ---------------------------------------------------------------------------------
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if with_usb_fifo:
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usb_pads = platform.request("usb_fifo")
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self.usb_phy = usb_phy = FT245PHYSynchronous(
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pads = usb_pads,
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clk_freq = sys_clk_freq,
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fifo_depth = 8,
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read_time = 128,
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write_time = 128,
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)
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if with_usb_fifo_loopback:
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usb_loopback = stream.SyncFIFO([("data", 32)], 2048, buffered=True)
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self.submodules += usb_loopback
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self.comb += [
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usb_phy.source.connect(usb_loopback.sink),
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usb_loopback.source.connect(usb_phy.sink),
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]
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else:
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self.comb += usb_phy.source.ready.eq(1) # Accept incoming stream to validate Host -> FPGA.
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analyzer_probes = usb_phy.get_litescope_probes()
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self.analyzer = LiteScopeAnalyzer(analyzer_probes,
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depth = 512,
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clock_domain = "usb",
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samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv"
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)
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# Debug -------------------------------------------------------------------------------
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egpio_pads = platform.request("egpio")
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self.comb += egpio_pads[0].eq(ClockSignal("sys"))
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self.comb += egpio_pads[1].eq(ClockSignal("usb"))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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leds_g = Signal(4)
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leds_r = Signal(4)
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self.comb += platform.request_all("led_g_n").eq(~leds_g)
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self.comb += platform.request_all("led_r_n").eq(~leds_r)
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self.leds = LedChaser(Cat(leds_g, leds_r), sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=limesdr_mini_v2.Platform, description="LiteX SoC on LimeSDR-Mini-V2.")
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parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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toolchain = args.toolchain,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
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if __name__ == "__main__":
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main()
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