90 lines
3.4 KiB
Python
Executable File
90 lines
3.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Michael Welling <mwelling@ieee.org>
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# This file is Copyright (c) 2020 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2020 Drew Fustini <drew@pdp7.com>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import hadbadge
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY
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from litedram.modules import AS4C32M8
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk8 = platform.request("clk8")
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platform.add_period_constraint(clk8, 1e9/8e6)
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk8, 8e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
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platform = hadbadge.Platform(toolchain=toolchain)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
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sdram_module = AS4C32M8(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
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help='gateware toolchain to use, diamond or trellis (default)')
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(toolchain=args.toolchain,
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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