178 lines
6.3 KiB
Python
178 lines
6.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxUSPPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk25", 0, Pins("AB11"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("W13"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("Y12"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("AA12"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("AB13"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("AA13"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("AE14"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("AE15"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("AG14"), IOStandard("LVCMOS33")),
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# Serial (no UART by default -> use J15 3 & 5)
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("serial", 0,
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Subsignal("tx", Pins("A11")),
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Subsignal("rx", Pins("A13")),
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IOStandard("LVCMOS33")
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),
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# MIPI 0
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("camera", 0,
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Subsignal("mclk", Pins("AG13"),IOStandard("LVCMOS33")),
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Subsignal("clkp", Pins("AC9")),
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Subsignal("clkn", Pins("AD9")),
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Subsignal("dp", Pins("AE9 AB8")),
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Subsignal("dn", Pins("AE8 AC8")),
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IOStandard("MIPI_DPHY")
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),
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("mipi_gpio", 0,
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Subsignal("gpio", Pins("AH14")),
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IOStandard("LVCMOS33")
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),
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("mipi_i2c", 0,
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Subsignal("scl", Pins("AH13")),
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Subsignal("sda", Pins("AE13")),
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IOStandard("LVCMOS33")
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),
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# MIPI 1
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("camera", 1,
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Subsignal("mclk", Pins("AC14"), IOStandard("LVCMOS33")),
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Subsignal("clkp", Pins("U9")),
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Subsignal("clkn", Pins("V9")),
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Subsignal("dp", Pins("U8 W8")),
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Subsignal("dn", Pins("V8 Y8")),
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IOStandard("MIPI_DPHY")
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),
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("mipi_gpio", 1,
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Subsignal("gpio", Pins("AD15")),
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IOStandard("LVCMOS33")
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),
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("mipi_i2c", 1,
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Subsignal("scl", Pins("AD14")),
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Subsignal("sda", Pins("AC13")),
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IOStandard("LVCMOS33")
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)
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("J12", {
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3: "F7", 4: "G8",
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5: "F6", 6: "G6",
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7: "D9", 8: "E9",
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9: "F5", 10: "G5",
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11: "E8", 12: "F8",
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13: "D5", 14: "E5",
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15: "C4", 16: "D4",
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17: "E3", 18: "E4",
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19: "F1", 20: "G1",
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21: "E2", 22: "F2",
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23: "D6", 24: "D7",
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25: "B9", 26: "C9",
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27: "A4", 28: "B4",
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29: "B6", 30: "C6",
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31: "A6", 32: "A7",
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33: "B8", 34: "C8",
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35: "A8", 36: "A9",
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}),
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("j15", {
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3: "A11", 4: "A12",
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5: "A13", 6: "B13",
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7: "A14", 8: "B14",
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9: "E13", 10: "E14",
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11: "A15", 12: "B15",
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13: "C13", 14: "C14",
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15: "B10", 16: "C11",
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17: "D14", 18: "D15",
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19: "F11", 20: "F12",
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21: "H13", 22: "H14",
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23: "G14", 24: "G15",
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25: "F10", 26: "G11",
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27: "H12", 28: "J12",
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29: "J14", 30: "K14",
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31: "K12", 32: "K13",
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33: "L13", 34: "L14",
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35: "G10", 36: "H11",
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})
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]
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# PSU config ---------------------------------------------------------------------------------------
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psu_config = {
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"PSU__DPAUX__PERIPHERAL__IO": "MIO 27 .. 30",
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"PSU__ENET3__PERIPHERAL__ENABLE": "1",
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"PSU__ENET3__GRP_MDIO__ENABLE": "1",
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"PSU__I2C1__PERIPHERAL__ENABLE": "1",
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"PSU__I2C1__PERIPHERAL__IO": "MIO 32 .. 33",
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"PSU__PCIE__PERIPHERAL__ENABLE": "1",
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"PSU__PCIE__PERIPHERAL__ROOTPORT_IO": "MIO 37",
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"PSU__USB0__REF_CLK_SEL": "Ref Clk1",
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"PSU__PCIE__DEVICE_PORT_TYPE": "Root Port",
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"PSU__PCIE__CLASS_CODE_SUB": "0x04",
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"SUBPRESET1": "DDR4_MICRON_MT40A256M16GE_083E",
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"PSU__QSPI__PERIPHERAL__ENABLE": "1",
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"PSU__QSPI__PERIPHERAL__DATA_MODE": "x4",
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"PSU__QSPI__GRP_FBCLK__ENABLE": "1",
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"PSU__SD1__PERIPHERAL__ENABLE": "1",
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"PSU__SD1__PERIPHERAL__IO": "MIO 46 .. 51",
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"PSU__SD1__GRP_CD__ENABLE": "1",
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"PSU__SD1__SLOT_TYPE": "SD 2.0",
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"PSU__TTC0__PERIPHERAL__ENABLE": "1",
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"PSU__TTC1__PERIPHERAL__ENABLE": "1",
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"PSU__TTC2__PERIPHERAL__ENABLE": "1",
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"PSU__TTC3__PERIPHERAL__ENABLE": "1",
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"PSU__DDRC__BUS_WIDTH": "32 Bit",
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"PSU__UART1__PERIPHERAL__ENABLE": "1",
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"PSU__UART1__PERIPHERAL__IO": "MIO 24 .. 25",
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"PSU__USB0__PERIPHERAL__ENABLE": "1",
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"PSU__USB0__RESET__ENABLE": "1",
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"PSU__USB0__RESET__IO": "MIO 44",
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"PSU__USB__RESET__MODE": "Shared MIO Pin",
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"PSU__USB3_0__PERIPHERAL__ENABLE": "1",
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"PSU__USB3_0__PERIPHERAL__IO": "GT Lane1",
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"PSU_BANK_0_IO_STANDARD": "LVCMOS18",
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"PSU_BANK_1_IO_STANDARD": "LVCMOS18",
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"PSU_BANK_2_IO_STANDARD": "LVCMOS18",
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"PSU__DISPLAYPORT__PERIPHERAL__ENABLE": "1",
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"PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL": "VPLL",
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"PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL": "RPLL",
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"PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL": "RPLL",
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"PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL": "APLL",
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}
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPPlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPPlatform.__init__(self, "xczu2cg-sfvc784-1-e", _io, _connectors, toolchain=toolchain)
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self.psu_config = psu_config
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def create_programmer(self, cable):
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return OpenFPGALoader("axu2cga", cable)
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def do_finalize(self, fragment):
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XilinxUSPPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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