74 lines
2.7 KiB
Python
74 lines
2.7 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Cam Link 4K PCB and IOs have been documented by @GregDavill and @ApertusOSCinema:
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# https://wiki.apertus.org/index.php/Elgato_CAM_LINK_4K
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# The FX3 exploration tool (and FPGA loader) has been developed by @ktemkin:
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# https://github.com/ktemkin/camlink-re
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeECP5Platform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk27", 0, Pins("B11"), IOStandard("LVCMOS25")),
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# Leds
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("user_led", 0, Pins("A6"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("A9"), IOStandard("LVCMOS25")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("A6")), # led0
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Subsignal("rx", Pins("A9")), # led1
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IOStandard("LVCMOS25")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"P2 L2 N1 P1 N5 M1 M3 N4",
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"L3 L1 P5 N2 N3"),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("C4 A3 B4"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("D3"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("C3"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("D5"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("B5"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"L5 F1 K4 G1 L4 H1 G2 J3",
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"D1 C1 E2 C2 F3 A2 E1 B1"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("K2 H4"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100"),
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IOStandard("SSTL135D_I")),
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Subsignal("clk_p", Pins("A4"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("E4"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("B3"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("C5"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeECP5Platform):
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default_clk_name = "clk27"
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default_clk_period = 1e9/27e6
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def __init__(self, toolchain="trellis", **kwargs):
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LatticeECP5Platform.__init__(self, "LFE5U-25F-8BG381C", _io, toolchain=toolchain, **kwargs)
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def do_finalize(self, fragment):
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LatticeECP5Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)
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