75 lines
2.0 KiB
Python
75 lines
2.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Work-In-Progress...
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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# TODO.
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# Debug.
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("debug", 0, Pins("A15"), IOStandard("LVCMOS33")),
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("debug", 1, Pins("C14"), IOStandard("LVCMOS33")),
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("debug", 2, Pins("B14"), IOStandard("LVCMOS33")),
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("debug", 3, Pins("A14"), IOStandard("LVCMOS33")),
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# Fan.
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("fan", 0, Pins(""), IOStandard("LVCMOS33")),
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# Flash.
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("flash_cs_n", 0, Pins("C23"), IOStandard("LVCMOS33")),
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("flash", 0,
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Subsignal("mosi", Pins("B24")),
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Subsignal("miso", Pins("A25")),
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Subsignal("vpp", Pins("B22")),
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Subsignal("hold", Pins("A22")),
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IOStandard("LVCMOS33")
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),
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# PCIe.
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("K21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("K6")),
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Subsignal("clk_n", Pins("K5")),
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Subsignal("rx_p", Pins("J4 L4 N4 R4")),
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Subsignal("rx_n", Pins("J3 L3 N3 R3")),
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Subsignal("tx_p", Pins("H2 K2 M2 P2")),
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Subsignal("tx_n", Pins("H1 K1 M1 P1"))
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),
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# DRAM (MT47H64M16).
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# HDMI Out.
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# TODO.
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# HDMI In.
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# TODO.
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "debug" # FIXME.
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default_clk_period = 1e9/100e6 # FIXME.
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain=toolchain)
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a70t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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