85 lines
3.1 KiB
Python
85 lines
3.1 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Andrew Dennison <andrew@motec.com.au>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.efinix.platform import EfinixPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk33", 0, Pins("C3"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), # net PLL_IN
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# Buttons
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("user_btn", 0, Pins("C5"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
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("user_btn", 1, Pins("C9"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
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# Leds
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("user_led", 0, Pins("B3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 1, Pins("J6"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 2, Pins("D7"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 3, Pins("D8"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("F3")), # net TXD
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Subsignal("rx", Pins("H2")), # net RXD
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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# SPIFlash (W25Q128JVSIM)
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("spiflash", 0,
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Subsignal("cs_n", Pins("J4")), # net SPI_SS
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Subsignal("clk", Pins("H4")), # net SPI_SCLK
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Subsignal("mosi", Pins("F4")), # net SPI_MOSI
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Subsignal("miso", Pins("H3")), # net SPI_MISO
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#Subsignal("wp", Pins("")),
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#Subsignal("hold", Pins("")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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# SDCard
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("spisdcard", 0,
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# All 4 SPI signals below have 10k pullup on dev board
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Subsignal("clk", Pins("J2")), # net SD_SCLK
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Subsignal("cs_n", Pins("G5")), # net SD_CS
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Subsignal("mosi", Pins("G4")), # net SD_DI
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Subsignal("miso", Pins("J3")), # net SD_DO
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Subsignal("det", Pins("G3")), # net CD2
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Misc("SLEW=FAST"),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Wacky PMOD pinout misunderstood by others too
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# resulting in this order: GPIOL_12,14,16,19,13,15,17,18
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("pmod", "G1 E2 C2 D3 F1 E1 D2 E3"),
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# GPIOR_020..28, 30..32, 34..36
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("j1", "F8 E7 F7 E6 F6 F5 G9 H9 J9 J8 G8 H8 J7 G6 H6"),
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# GPIOR_19..10, 08..05, 03, 01, 00
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("j2", "E8 D9 D8 D7 C9 B9 D6 C8 B8 A9 A8 C7 C6 B6 A6 B5 A5"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(EfinixPlatform):
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default_clk_name = "clk33"
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default_clk_period = 1e9/33.333e6
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def __init__(self, toolchain="efinity"):
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EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return OpenFPGALoader("xyloni_spi")
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def do_finalize(self, fragment):
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EfinixPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk33", loose=True), 1e9/33.333e6)
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