89 lines
3.0 KiB
Python
89 lines
3.0 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2016-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk100", 0, Pins("R2"), IOStandard("LVCMOS33")),
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# Leds.
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("user_led", 0, Pins("V17"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("U17"), IOStandard("LVCMOS33")),
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# Serial.
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("serial", 0,
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Subsignal("tx", Pins("U4")),
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Subsignal("rx", Pins("V4")),
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IOStandard("LVCMOS33"),
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),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("M1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("D6")),
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Subsignal("clk_n", Pins("D5")),
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Subsignal("rx_p", Pins("E4")),
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Subsignal("rx_n", Pins("E3")),
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Subsignal("tx_p", Pins("H2")),
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Subsignal("tx_n", Pins("H1"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("M1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("D6")),
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Subsignal("clk_n", Pins("D5")),
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Subsignal("rx_p", Pins("E4 A4 C4 G4")),
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Subsignal("rx_n", Pins("E3 A3 C3 G3")),
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Subsignal("tx_p", Pins("H2 F2 D2 B2")),
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Subsignal("tx_n", Pins("H1 F1 D1 B1"))
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),
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# USB-FIFO.
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("usb_fifo_clock", 0, Pins("E13"), IOStandard("LVCMOS33")),
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("usb_fifo", 0,
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Subsignal("rst", Pins("U15")),
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Subsignal("data", Pins(
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"B9 A9 C9 A10 B10 B11 A12 B12",
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"A13 A14 B14 A15 B15 B16 A17 B17",
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"C17 C18 D18 E17 E18 E16 F18 F17",
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"G17 H18 D13 C14 D14 D15 C16 D16")),
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Subsignal("be", Pins("L18 M17 N18 N17")),
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Subsignal("rxf_n", Pins("R18")),
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Subsignal("txe_n", Pins("P18")),
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Subsignal("rd_n", Pins("R16")),
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Subsignal("wr_n", Pins("T18")),
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Subsignal("oe_n", Pins("T15")),
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Subsignal("siwua", Pins("R17")),
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IOStandard("LVCMOS33"),
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Misc("SLEW=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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Xilinx7SeriesPlatform.__init__(self, "xc7a35t-csg325-2", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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