125 lines
4.3 KiB
Python
125 lines
4.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeECP5Platform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk40", 0, Pins("A9"), IOStandard("LVCMOS33")),
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# Leds.
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("led_g_n", 0, Pins("R16"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
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("led_g_n", 1, Pins("M18"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO4.
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("led_g_n", 2, Pins("T17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO6.
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("led_r_n", 0, Pins("V17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
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("led_r_n", 1, Pins("R18"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO5.
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("led_r_n", 2, Pins("R17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO7.
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# Revision.
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("revision", 0,
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Subsignal("hardware", Pins("D4 M2 N4 J3")),
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Subsignal("bom", Pins("N1 M1 N2")),
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IOStandard("LVCMOS25")
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),
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# GPIO.
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("gpio", 0, Pins("N15 N18 N16 N17 M18 R18 T17 R17"), IOStandard("LVCMOS33")),
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("egpio", 0, Pins("A10 A8"), IOStandard("LVCMOS33")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("U17")),
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Subsignal("clk", Pins("U16")),
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Subsignal("miso", Pins("U18")),
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Subsignal("mosi", Pins("T18")),
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IOStandard("LVCMOS33"),
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),
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# I2C.
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("i2c", 0,
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Subsignal("scl", Pins("C10"), Misc("OPENDRAIN=ON")),
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Subsignal("sda", Pins("B9"), Misc("OPENDRAIN=ON")),
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IOStandard("LVCMOS33"),
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),
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# SPI.
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("spi", 0,
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# SPI.
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Subsignal("clk", Pins("M3")),
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Subsignal("lms_cs_n", Pins("N3")),
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Subsignal("dac_cs_n", Pins("L4")),
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Subsignal("mosi", Pins("L3")),
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Subsignal("miso", Pins("K3")),
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IOStandard("LVCMOS25"),
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),
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# Temperature Sensor.
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("lms75_os", 0, Pins("K2"), IOStandard("LVCMOS25")),
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# USB-FIFO.
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("usb_fifo_clk", 0, Pins("D17"), IOStandard("LVCMOS33")),
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("usb_fifo", 0,
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Subsignal("rst_n", Pins("M17")),
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Subsignal("data", Pins(
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"A13 B12 B15 C12 A16 A12 D18 B17",
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"F15 D16 D15 C13 H18 B13 J18 A15",
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"B18 C18 A17 K18 C15 L18 F18 C16",
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"G16 D13 G18 F16 C17 F17 K15 K17")),
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Subsignal("be", Pins("L15 J17 K16 H17")),
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Subsignal("rxf_n", Pins("H16")),
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Subsignal("txe_n", Pins("M16")),
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Subsignal("rd_n", Pins("H15")),
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Subsignal("wr_n", Pins("J16")),
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Subsignal("oe_n", Pins("L16")),
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IOStandard("LVCMOS33"),
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),
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# RF-IC / LMS7002M.
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("lms7002m", 0,
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# Control.
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Subsignal("pwrdwn_n", Pins("C8")),
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Subsignal("rxen", Pins("D6")),
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Subsignal("txen", Pins("B7")),
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# RX-Interface (LMS -> FPGA).
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Subsignal("diq1", Pins("J2 L1 K1 K4 G3 F4 J1 H1 G4 F2 G1 H2")),
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Subsignal("txnrx1", Pins("F1")),
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Subsignal("iqsel1", Pins("F3")),
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Subsignal("mclk1", Pins("H4")),
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Subsignal("fclk1", Pins("H3")),
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# RX-Interface (FPGA -> LMS).
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Subsignal("diq2", Pins("A3 C2 A2 B4 C3 B2 D3 B1 A4 C1 C7 A6")),
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Subsignal("txnrx2", Pins("B6")),
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Subsignal("iqsel2", Pins("C4")),
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Subsignal("mclk2", Pins("D2")),
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Subsignal("fclk2", Pins("D1")),
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# IOStandard/Slew Rate.
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IOStandard("LVCMOS25"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeECP5Platform):
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default_clk_name = "clk40"
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default_clk_period = 1e9/40e6
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def __init__(self, device="LFE5U", toolchain="trellis", **kwargs):
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assert device in ["LFE5U"]
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LatticeECP5Platform.__init__(self, device + "-45F-8MG285C", _io, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_limesdr_mini_v2.cfg")
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def do_finalize(self, fragment):
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self.add_period_constraint(self.lookup_request("clk40", loose=True), 1e9/40e6)
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