160 lines
4.9 KiB
Python
160 lines
4.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io_vx = [
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# Clock
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("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("C1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("E1"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("G1"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("C1"), IOStandard("LVCMOS33")),
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Subsignal("g", Pins("E1"), IOStandard("LVCMOS33")),
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Subsignal("b", Pins("G1"), IOStandard("LVCMOS33")),
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),
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# Buttons
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("user_btn", 0, Pins("C2"), IOStandard("LVCMOS33")),
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# DDR3L
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("ddram", 0,
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Subsignal("a", Pins(
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"R15 L13 P14 R14 L12 T14 N11 T13",
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"P12 T15 C14 M13 E14 R13 M14 D14"),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("N16 K13 P16"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("L16"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("M16"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("P15"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("M15"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("F13 J13"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"F14 E16 F12 F15 G13 B16 G12 B15",
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"J14 J16 K15 K14 H14 K16 H13 J15"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("D16 G16"), IOStandard("SSTL135D_I"),
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Misc("TERMINATION=OFF DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("C16"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("K12"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("L15"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("R12"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST")
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),
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# USB-C
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("usb", 0,
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Subsignal("d_p", Pins("T6")),
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Subsignal("d_n", Pins("R6")),
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Subsignal("pullup", Pins("R7")),
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IOStandard("LVCMOS33")
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),
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# DUAL USB HOST
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("usb_host", 0,
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Subsignal("dp", Pins("R4 P1")),
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Subsignal("dm", Pins("T3 R1")),
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IOStandard("LVCMOS33")
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),
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# ETHERNET
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins("M1")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rx_data", Pins("N1 P2"), Misc("PULLMODE=UP")),
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Subsignal("tx_data", Pins("T2 R2")),
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Subsignal("tx_en", Pins("P3")),
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Subsignal("crs_dv", Pins("M3"), Misc("PULLMODE=UP")),
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Subsignal("rst_n", Pins("N4")),
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IOStandard("LVCMOS33")
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),
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# DEBUG UART
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("serial", 0,
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Subsignal("tx", Pins("B1")),
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Subsignal("rx", Pins("B2")),
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IOStandard("LVCMOS33")
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),
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# SPI
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("spiflash", 0,
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Subsignal("cs_n", Pins("N8")),
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Subsignal("miso", Pins("T7")),
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Subsignal("mosi", Pins("T8")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_io_v0 = [
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# SD card w/ SD-mode interface
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("sdcard", 0,
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Subsignal("cd", Pins("A5")),
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Subsignal("clk", Pins("B4")),
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Subsignal("cmd", Pins("A3"), Misc("PULLMODE=UP")),
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Subsignal("data", Pins("A4 B5 A2 B3"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33")
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),
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# SD card w/ SPI interface
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("spisdcard", 0,
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Subsignal("clk", Pins("B4")),
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Subsignal("mosi", Pins("A3")),
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Subsignal("cs_n", Pins("B3")),
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Subsignal("miso", Pins("A4")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_vx = [
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("PMODA", "K3 J2 J3 F1 K2 K1 J1 G2"),
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("PMODB", "N5 M5 T4 P4 N6 M6 R5 P5"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, revision="v0", device="12F", toolchain="trellis", **kwargs):
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assert revision in ["v0"]
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assert device in ["12F", "25F", "45F", "85F"]
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self.revision = revision
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io = _io_vx
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connectors = _connectors_vx
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if revision == "v0": io += _io_v0
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LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, cable):
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return OpenFPGALoader(cable=cable)
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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