63 lines
2.1 KiB
Python
63 lines
2.1 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
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# Copyright (c) 2021 Michael T. Mayers <michael@tweakoz.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("N14"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("M1"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("A14"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A13"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("N11")), # BDBUS1
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Subsignal("rx", Pins("E11")), # BDBUS0
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IOStandard("LVCMOS33")
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),
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# SRAM
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("issiram", 0,
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Subsignal("addr", Pins(
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"M4 N3 N4 P3 M5 E5 D5 D3",
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"B7 B4 J4 H4 H3 G4 E6 A7",
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"A5 A4 C4"),
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IOStandard("LVCMOS33")),
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Subsignal("data", Pins(
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"L5 L3 L4 R2 F3 F4 E3 D6"),
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IOStandard("LVCMOS33")),
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Subsignal("wen", Pins("R1"), IOStandard("LVCMOS33")),
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Subsignal("cen", Pins("M6"), IOStandard("LVCMOS33")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7a35tftg256-1", _io, _connectors, toolchain=toolchain)
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def do_finalize(self,fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), self.default_clk_period)
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