103 lines
3.7 KiB
Python
103 lines
3.7 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# iCESugar FPGA: https://www.aliexpress.com/item/4001201771358.html
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeiCE40Platform
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from litex.build.lattice.programmer import IceSugarProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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# Leds R / G / B
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("user_led_n", 0, Pins("40"), IOStandard("LVCMOS33")),
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("user_led_n", 1, Pins("39"), IOStandard("LVCMOS33")),
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("user_led_n", 2, Pins("41"), IOStandard("LVCMOS33")),
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# RGB led, active-low, alias for Leds
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("rgb_led", 0,
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Subsignal("r", Pins("40")),
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Subsignal("g", Pins("39")),
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Subsignal("b", Pins("31")),
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IOStandard("LVCMOS33"),
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),
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# Switches / jumper-attached to PMOD4
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("user_sw", 0, Pins("18"), IOStandard("LVCMOS18")),
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("user_sw", 1, Pins("19"), IOStandard("LVCMOS18")),
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("user_sw", 2, Pins("20"), IOStandard("LVCMOS18")),
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("user_sw", 3, Pins("21"), IOStandard("LVCMOS18")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("4")),
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Subsignal("tx", Pins("6"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
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),
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# USB
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("usb", 0,
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Subsignal("d_p", Pins("10")),
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Subsignal("d_n", Pins("9")),
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Subsignal("pullup", Pins("11")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Pin order similar to iCEBreaker to allow PMODs reuse.
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("PMOD1", "10 6 3 48 9 4 2 47"),
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("PMOD2", "46 44 42 37 45 43 38 36"),
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("PMOD3", "34 31 27 25 32 28 26 23"),
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("J7", "48 - 3 47 - 2"), # Numbering similar to PMODS: 0: Marked pin.
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]
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# PMODS --------------------------------------------------------------------------------------------
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def led_pmod_io_v11(pmod, offset=0):
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return [
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# LED PMOD: https://www.aliexpress.com/item/1005001504777342.html
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# Contrary to the supplied schematic, the two nibbles seem to be swapped on the board.
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("user_led_n", offset + 0, Pins(f"{pmod}:4"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 1, Pins(f"{pmod}:5"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 2, Pins(f"{pmod}:6"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 3, Pins(f"{pmod}:7"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 4, Pins(f"{pmod}:0"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 5, Pins(f"{pmod}:1"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 6, Pins(f"{pmod}:2"), IOStandard("LVCMOS33")),
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("user_led_n", offset + 7, Pins(f"{pmod}:3"), IOStandard("LVCMOS33")),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeiCE40Platform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, toolchain="icestorm"):
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LatticeiCE40Platform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return IceSugarProgrammer()
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def do_finalize(self, fragment):
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LatticeiCE40Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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