129 lines
4.8 KiB
Python
129 lines
4.8 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
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# Leds (only a single rgb led, aliased here also)
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("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("U20"), IOStandard("LVCMOS33")),
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# RGB led, active-low
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("rgb_led", 0,
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Subsignal("r", Pins("AB21")),
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Subsignal("g", Pins("AB22")),
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Subsignal("b", Pins("U20")),
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IOStandard("LVCMOS33"),
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),
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# SPIFlash
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("flash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("hold", Pins("R21")),
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Subsignal("rst_n", Pins("R19")),
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IOStandard("LVCMOS33")
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),
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("flash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("T19")),
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Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
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IOStandard("LVCMOS33")
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),
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# TPM
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("tpm", 0,
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Subsignal("clk", Pins("W20")),
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Subsignal("rst_n", Pins("V19")),
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Subsignal("cs_n", Pins("Y18")),
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Subsignal("mosi", Pins("Y19")),
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Subsignal("miso", Pins("V18")),
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IOStandard("LVCMOS33"),
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B8")),
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Subsignal("rx_n", Pins("A8")),
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Subsignal("tx_p", Pins("B4")),
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Subsignal("tx_n", Pins("A4"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B8 D11 B10 D9")),
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Subsignal("rx_n", Pins("A8 C11 A10 C9")),
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Subsignal("tx_p", Pins("B4 D5 B6 D7")),
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Subsignal("tx_n", Pins("A4 C5 A6 C7"))
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"U6 T5 Y6 T6 V2 T4 Y2 R2",
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"Y1 R4 W5 W1 AA6 U2"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
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"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")),
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Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain=toolchain)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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