163 lines
5.3 KiB
Python
163 lines
5.3 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("E1"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("F3"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("J6"), IOStandard("3.3-V LVTTL")),
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# SPIFlash (W25Q64)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("D2")),
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Subsignal("clk", Pins("H1")),
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Subsignal("mosi", Pins("C1")),
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Subsignal("miso", Pins("H2")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("P2"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"R7 T7 R8 T8 R6 T5 R5 T4",
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"R4 T3 T6 R3 T2")),
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Subsignal("ba", Pins("N8 L8")),
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Subsignal("cs_n", Pins("P8")),
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Subsignal("cke", Pins("R1")),
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Subsignal("ras_n", Pins("M8")),
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Subsignal("cas_n", Pins("M7")),
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Subsignal("we_n", Pins("P6")),
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Subsignal("dq", Pins(
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"K5 L3 L4 K6 N3 M6 P3 N5",
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"N2 N1 L1 L2 K1 K2 J1 J2")),
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Subsignal("dm", Pins("N6 P1")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U7 and J3 is U8
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_connectors = [
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("J2", {
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# odd row even row
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7: "G1", 8: "G2",
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9: "D1", 10: "C2",
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11: "B1", 12: "F5",
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13: "D3", 14: "C3",
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15: "B3", 16: "A3",
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17: "B4", 18: "A4",
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19: "E5", 20: "A2",
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21: "D4", 22: "E6",
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23: "C6", 24: "D6",
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25: "B5", 26: "A5",
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27: "B6", 28: "A6",
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29: "B7", 30: "A7",
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31: "D8", 32: "C8",
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33: "D9", 34: "C9",
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35: "B8", 36: "A8",
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37: "B9", 38: "A9",
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39: "E9", 40: "E8",
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41: "E11", 42: "E10",
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43: "A10", 44: "B10",
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45: "D12", 46: "D11",
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47: "B11", 48: "A11",
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49: "B12", 50: "A12",
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51: "B13", 52: "A13",
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53: "B14", 54: "A14",
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55: "D14", 56: "C14",
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57: "B16", 58: "A15",
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59: "C16", 60: "C15",
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}),
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("J3", {
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# odd row even row
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7: "R9", 8: "T9",
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9: "R10", 10: "T10",
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11: "R11", 12: "T11",
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13: "R12", 14: "T12",
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15: "N9", 16: "M9",
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17: "M10", 18: "P9",
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19: "P11", 20: "N11",
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21: "R13", 22: "T13",
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23: "T15", 24: "T14",
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25: "N12", 26: "M11",
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27: "R14", 28: "N13",
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29: "N14", 30: "P14",
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31: "P16", 32: "R16",
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33: "N16", 34: "N15",
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35: "M16", 36: "M15",
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37: "L16", 38: "L15",
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39: "P15", 40: "M12",
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41: "L14", 42: "L13",
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43: "K16", 44: "K15",
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45: "K12", 46: "J12",
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47: "J14", 48: "J13",
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49: "K11", 50: "J11",
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51: "G11", 52: "F11",
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53: "F13", 54: "F14",
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55: "F10", 56: "F9",
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57: "E16", 58: "E15",
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59: "D16", 60: "D15",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
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Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
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Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
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),
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]
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def __init__(self, toolchain="quartus", with_daughterboard=False):
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device = "10CL006YU256C8G"
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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else:
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io += self.core_resources
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AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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if with_daughterboard:
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# an ethernet pin takes K22, so make it available
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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# Generate PLL clock in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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