172 lines
5.9 KiB
Python
172 lines
5.9 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Kazumoto Kojima
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# Copyright (c) 2023 Ruurd Keizer <ruurdk@hotmail.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("F22"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("U26"), IOStandard("LVCMOS33")),
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# Switches
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("sw2", 0, Pins("U26"), IOStandard("LVCMOS33")), # cpu_reset
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("sw3", 0, Pins("V26"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("R26"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("P26"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("N26"), IOStandard("LVCMOS33")),
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# The board does not have a USB serial connected to the FPGA,
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# so you will have to either connect through the rpi uart through gpio pins (and use serial uart hw or software),
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# or attach an USB to serial adapter on JP5 pins (default)
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("JP5_serial", 0,
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Subsignal("tx", Pins("JP5:7")),
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Subsignal("rx", Pins("JP5:8")),
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IOStandard("LVCMOS33")
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),
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#("gpio_serial", 0,
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# Subsignal("tx", Pins("GPIO:14")),
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# Subsignal("rx", Pins("GPIO:15")),
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# IOStandard("LVCMOS33")
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# )
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# SPIFlash
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# S25FL128L
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("C23")),
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Subsignal("clk", Pins("C8")),
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Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# MT41J128M16JT-125K
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("ddram", 0,
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Subsignal("a", Pins("AF5 AF2 AD6 AC6 AD4 AB6 AE2 Y5 AA4 AE6 AE3 AD5 AB4 Y6"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AD3 AE1 AE5"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AC3"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AC4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AF4"), IOStandard("SSTL15")),
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#Subsignal("cs_n", Pins("--"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("V1 V3"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"W1 V2 Y1 Y3 AC2 Y2 AB2 AA3",
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"U1 V4 U6 W3 V6 U2 U7 U5"),
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IOStandard("SSTL15")), # _T_DCI")),
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Subsignal("dqs_p", Pins("AB1 W6"), IOStandard("DIFF_SSTL15")), # _T_DCI")),
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Subsignal("dqs_n", Pins("AC1 W5"), IOStandard("DIFF_SSTL15")), # _T_DCI")),
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Subsignal("clk_p", Pins("AA5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AB5"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AD1"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AF3"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("W4"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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),
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# ("csi", 0,
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# Subsignal("csi", Pins("")),
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# IOStandard("LVCMOS33")
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# ),
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]
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_connectors = [
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# 25x2 header
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("JP5", {
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# odd row even row
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5: "AD21", 6: "AE21",
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7: "AE22", 8: "AF22",
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9: "AE23", 10: "AF23",
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11: "V21", 12: "W21",
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13: "Y22", 14: "AA22",
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15: "AF24", 16: "AF25",
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17: "AB21", 18: "AC21",
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19: "AB22", 20: "AC22",
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21: "AD23", 22: "AD24",
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23: "AC23", 24: "AC24",
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25: "AD25", 26: "AE25",
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27: "AA23", 28: "AB24",
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29: "AA25", 30: "AB25",
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31: "Y23", 32: "AA24",
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33: "AD26", 34: "AE26",
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35: "AB26", 36: "AC26",
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37: "W23", 38: "W24",
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39: "Y25", 40: "Y26",
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41: "W25", 42: "W26",
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43: "V23", 44: "V24",
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45: "U24", 46: "U25",
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}),
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# PMOD_1
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("J11", {
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1: "C16", 7: "B16",
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2: "A17", 8: "B17",
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3: "A18", 9: "A19",
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4: "A20", 10: "B20",
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}),
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# PMOD_2
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("J12", {
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1: "E21", 7: "E22",
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2: "D23", 8: "D24",
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3: "D25", 9: "E25",
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4: "F23", 10: "F24",
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}),
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# PMOD_3
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("J13", {
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1: "A24", 7: "A23",
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2: "B26", 8: "B25",
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3: "D26", 9: "C26",
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4: "F25", 10: "E26",
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}),
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# defining the pins to the rpi's GPIO as virtual connector - signals will still depend on gpio functions
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("GPIO", {
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0: "C12", 1: "B11", 2: "C18", 3: "D18", 4: "E18", 5: "C11", 6: "D10", 7: "B12", 8: "A12", 9: "D14",
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10: "C13", 11: "D13", 12: "A10", 13: "E10", 14: "C17", 15: "A15", 16: "B10", 17: "D16", 18: "B15", 19: "B9",
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20: "A9", 21: "A8", 22: "C14", 23: "A14", 24: "B14", 25: "A13", 26: "C9", 27: "D15",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="vivado"):
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device = "xc7k325tffg676-1"
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io = _io
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connectors = _connectors
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XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.90 [get_iobanks 33]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7k325t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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