121 lines
4.7 KiB
Python
121 lines
4.7 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Pepijn de Vos <pepijndevos@gmail.com>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("63"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("77"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("86"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("85"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("84"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("83"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("82"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("81"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("80"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("79"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("16"), IOStandard("LVCMOS33")),
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("51"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("49"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("53"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("48"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("54"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("50"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("51")),
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Subsignal("clk", Pins("49")),
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Subsignal("dq", Pins("48 53 54 50")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash (FTDI Chip)
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("spiflash", 1,
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Subsignal("cs_n", Pins("13"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("14"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("15"), IOStandard("LVCMOS33")),
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),
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# SDRAM (embedded in SIP, requires specific IO naming)
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("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_wen_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_dqm", 0, Pins(2), IOStandard("LVCMOS33")),
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("O_sdram_addr", 0, Pins(12), IOStandard("LVCMOS33")),
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("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")),
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("IO_sdram_dq", 0, Pins(16), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod", "47 41 38 40 36 42 39 37"),
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]
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# PMODs --------------------------------------------------------------------------------------------
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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# - https://github.com/antmicro/arty-expansion-board
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULL_MODE=UP")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULL_MODE=UP")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULL_MODE=UP")),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULL_MODE=UP")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULL_MODE=UP")),
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("cd", Pins(f"{pmod}:6")),
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IOStandard("LVCMOS33"),
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),
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]
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_sdcard_pmod_io = sdcard_pmod_io("pmod")
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, toolchain="gowin"):
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GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1NR-9")
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def create_programmer(self):
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return OpenFPGALoader("littleBee")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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