88 lines
3.3 KiB
Python
Executable File
88 lines
3.3 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteX-Boards.
|
|
#
|
|
# Copyright (c) 2022 Alex Petrov <sysman@sysman.net>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
from migen import *
|
|
|
|
from litex.gen import *
|
|
|
|
from litex_boards.platforms import aliexpress_xc7k420t
|
|
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.cores.led import LedChaser
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(LiteXModule):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.rst = Signal()
|
|
self.cd_sys = ClockDomain()
|
|
|
|
# Clk / Rst.
|
|
clk100 = platform.request("clk100")
|
|
rst_n = platform.request("user_btn_k3") # FIXME: Why not cpu_reset?
|
|
|
|
# PLL.
|
|
self.pll = pll = S7MMCM(speedgrade=-1)
|
|
self.comb += pll.reset.eq(~rst_n | self.rst)
|
|
pll.register_clkin(clk100, 100e6)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCCore):
|
|
def __init__(self, sys_clk_freq=100e6,
|
|
with_led_chaser = True,
|
|
with_spi_flash = False,
|
|
**kwargs):
|
|
platform = aliexpress_xc7k420t.Platform()
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# SoCCore ----------------------------------_-----------------------------------------------
|
|
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AliExpress u420t", **kwargs)
|
|
|
|
# SPI Flash --------------------------------------------------------------------------------
|
|
if with_spi_flash:
|
|
from litespi.modules import N25Q256
|
|
from litespi.opcodes import SpiNorFlashOpCodes as Codes
|
|
self.add_spi_flash(mode="4x", module=W25Q256(Codes.READ_1_1_4))
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
if with_led_chaser:
|
|
self.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
def main():
|
|
from litex.build.parser import LiteXArgumentParser
|
|
parser = LiteXArgumentParser(platform=aliexpress_xc7k420t.Platform, description="LiteX SoC on AliExpress u420t.")
|
|
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
|
|
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.")
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(
|
|
sys_clk_freq = args.sys_clk_freq,
|
|
**parser.soc_argdict
|
|
)
|
|
builder = Builder(soc, **parser.builder_argdict)
|
|
if args.build:
|
|
builder.build(**parser.toolchain_argdict)
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(obuilder.get_bitstream_filename(mode="sram"))
|
|
|
|
if __name__ == "__main__":
|
|
main()
|