127 lines
4.7 KiB
Python
Executable File
127 lines
4.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Fabien Caura <fabien@acathla.tk>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import gadgetfactory_papilio_pro
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT48LC4M16
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from litedram.phy import s6ddrphy, GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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self.cd_vga = ClockDomain()
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# # #
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# Clk / Rst
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clk32 = platform.request("clk32")
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# PLL
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self.pll = pll = S6PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk32, 32e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_vga, 40e6)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=80e6,
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with_led_chaser = True,
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with_video_terminal = False,
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**kwargs):
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platform = gadgetfactory_papilio_pro.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
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kwargs["cpu_variant"] = "minimal"
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Papilio Pro", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC4M16(sys_clk_freq, "1:2"),
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l2_cache_size = 0
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Video Terminal ---------------------------------------------------------------------------
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if with_video_terminal:
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self.platform.add_extension(gadgetfactory_papilio_pro._arcade_megawing)
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self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform, description="LiteX SoC on Papilio Pro.")
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parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_video_terminal = args.with_video_terminal,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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