194 lines
7.5 KiB
Python
Executable File
194 lines
7.5 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Sylvain Munaut <tnt@246tNt.com>
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# Copyright (c) 2023 Michael Welling <mwelling@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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# This target file provides a minimal LiteX SoC for the ICE-V with a CPU,
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# its ROM (in SPI PSRAM), its SRAM, close to the others LiteX targets.
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex_boards.platforms import ice_v_wireless
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from litex.soc.cores.ram import Up5kSPRAM
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# PSRAM flash emulation ----------------------------------------------------------------------------------------------
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from litespi.spi_nor_flash_module import SpiNorFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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class PSRAM(SpiNorFlashModule):
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manufacturer_id = 0x000d
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device_id = 0x0000
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name = "PSRAM"
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total_size = 8388608 # bytes
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page_size = 1024 # bytes
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total_pages = 8192
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supported_opcodes = [
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Codes.READ_1_1_1,
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Codes.READ_1_1_1_FAST,
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Codes.READ_1_4_4,
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Codes.PP_1_1_1,
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]
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dummy_bits = 8
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq=48e6, with_usb_pll=False):
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assert not with_usb_pll or sys_clk_freq == 48e6
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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# # #
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# Clk/Rst
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clk12 = platform.request("clk12")
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rst_n = platform.request("user_btn_n")
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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if with_usb_pll:
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self.cd_usb_12 = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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locked = Signal()
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self.specials.pll = pll = Instance("SB_PLL40_2F_PAD",
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i_PACKAGEPIN = clk12,
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i_RESETB = rst_n,
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i_BYPASS = C(0),
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# o_PLLOUTGLOBALA = self.cd_sys.clk,
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o_PLLOUTGLOBALA = self.cd_usb_48.clk,
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o_PLLOUTGLOBALB = self.cd_usb_12.clk,
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o_LOCK = locked,
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# Create a 48 MHz PLL clock...
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p_FEEDBACK_PATH = "SIMPLE",
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p_PLLOUT_SELECT_PORTA = "GENCLK",
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p_PLLOUT_SELECT_PORTB = "SHIFTREG_0deg",
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p_DIVR = 0,
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p_DIVF = 63,
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p_DIVQ = 4,
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p_FILTER_RANGE = 1,
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)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~locked)
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platform.add_period_constraint(self.cd_sys.clk, 48e6)
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platform.add_period_constraint(self.cd_usb_48.clk, 48e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 12e6)
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self.comb += [
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self.cd_sys.clk.eq(self.cd_usb_48.clk),
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]
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else:
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self.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
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self.comb += pll.reset.eq(~rst_n) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, bios_flash_offset, sys_clk_freq=24e6, revision="v0", with_led_chaser=True, **kwargs):
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platform = ice_v_wireless.Platform(revision=revision)
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# CRG --------------------------------------------------------------------------------------
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with_usb_acm = kwargs["uart_name"] == "usb_acm"
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if with_usb_acm:
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sys_clk_freq = 48e6
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self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=with_usb_acm)
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# SoCCore ----------------------------------------------------------------------------------
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ICE-V Wireless", **kwargs)
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# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
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self.spram = Up5kSPRAM(size=128*kB)
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self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
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self.bus.add_region("sram", SoCRegion(
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origin = self.bus.regions["psram"].origin + 0*kB,
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size = 64*kB,
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linker = True)
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)
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if not self.integrated_main_ram_size:
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self.bus.add_region("main_ram", SoCRegion(
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origin = self.bus.regions["psram"].origin + 64*kB,
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size = 64*kB,
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linker = True)
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)
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# LED Chaser --------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq,
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polarity = 1)
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# PSRAM emulating flash --------------------------------------------------------------------
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self.add_spi_flash(mode="1x", module=PSRAM(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=ice_v_wireless.Platform, description="LiteX SoC on ICE-V Wireless.")
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parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash.")
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parser.add_target_argument("--revision", default="v0", help="Board revision.")
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = args.sys_clk_freq,
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revision = args.revision,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if __name__ == "__main__":
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main()
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