132 lines
4.7 KiB
Python
Executable File
132 lines
4.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Omkar Bhilare <ombhilare999@gmail.com>
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# Copyright (c) 2021 Michael Welling <mwelling@ieee.org>
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# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Krote FPGA board: https://github.com/machdyne/krote
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#
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# TODO:
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# - add support for QQSPI PSRAM (32MB) pmod
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# - add support for SD card pmod
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#
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import os
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import sys
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from migen import *
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from litex.gen import *
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from litex.build.io import CRG
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from litex_boards.platforms import machdyne_krote
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.cores.led import LedChaser
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from migen.genlib.resetsync import AsyncResetSynchronizer
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kB = 1024
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mB = 1024*kB
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# _CRG ---------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain(reset_less=True)
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# Clk/Rst
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk100)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# Sys Clk
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self.pll = pll = iCE40PLL()
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x20000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
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platform = machdyne_krote.Platform()
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# Disable Integrated ROM since too large for iCE40.
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kwargs["integrated_rom_size"] = 0
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kwargs["integrated_sram_size"] = 4*kB
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Kr\xf6te",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q32
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=machdyne_krote.Platform, description="LiteX SoC on Kr\xf6te.")
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parser.add_argument("--bios-flash-offset", default="0x021000", help="BIOS offset in SPI Flash (default: 0x21000)")
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parser.add_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-led-chaser", action="store_true", help="Enable LED Chaser.")
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if __name__ == "__main__":
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main()
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