194 lines
8.7 KiB
Python
Executable File
194 lines
8.7 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import radiona_ulx3s
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoHDMIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.spi import SPIMaster
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from litex.soc.cores.gpio import GPIOOut
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk25 = platform.request("clk25")
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rst = platform.request("rst")
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# PLL
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# USB PLL
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if with_usb_pll:
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self.usb_pll = usb_pll = ECP5PLL()
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self.comb += usb_pll.reset.eq(rst | self.rst)
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usb_pll.register_clkin(clk25, 25e6)
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self.cd_usb_12 = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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# Video PLL
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if with_video_pll:
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self.video_pll = video_pll = ECP5PLL()
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self.comb += video_pll.reset.eq(rst | self.rst)
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video_pll.register_clkin(clk25, 25e6)
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi, 25e6, margin=0)
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video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# Prevent ESP32 from resetting FPGA
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self.comb += platform.request("wifi_gpio0").eq(1)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", sys_clk_freq=50e6,
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sdram_module_cls = "MT48LC16M16",
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sdram_rate = "1:1",
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with_led_chaser = True,
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_spi_flash = False,
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**kwargs):
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platform = radiona_ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
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with_video_pll = with_video_terminal or with_video_framebuffer
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self.crg = _CRG(platform, sys_clk_freq, with_usb_pll, with_video_pll, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ULX3S", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import IS25LP128
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=IS25LP128(Codes.READ_1_1_4))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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def add_oled(self):
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pads = self.platform.request("oled_spi")
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pads.miso = Signal()
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self.oled_spi = SPIMaster(pads, 8, self.sys_clk_freq, 8e6)
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self.oled_spi.add_clk_divider()
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self.oled_ctl = GPIOOut(self.platform.request("oled_ctl"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=radiona_ulx3s.Platform, description="LiteX SoC on ULX3S")
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parser.add_target_argument("--device", default="LFE5U-45F", help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).")
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parser.add_target_argument("--revision", default="2.0", help="Board revision (2.0 or 1.7).")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module (MT48LC16M16, AS4C32M16 or AS4C16M16).")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_target_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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args = parser.parse_args()
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soc = BaseSoC(
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device = args.device,
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revision = args.revision,
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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sdram_module_cls = args.sdram_module,
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sdram_rate = args.sdram_rate,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_spi_flash = args.with_spi_flash,
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**parser.soc_argdict)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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if args.with_oled:
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soc.add_oled()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
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if __name__ == "__main__":
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main()
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