111 lines
4.0 KiB
Python
Executable File
111 lines
4.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use
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# ---------
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# 1) Update CH552 firmware: https://qiita.com/ciniml/items/05ac7fd2515ceed3f88d
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# 2) Build/Load design: ./sipeed_tang_nano.py --csr-csv=csr.csv --build --load
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# 3) Patch litex_server (CH552 firmware seems to require receiving a few bytes before
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# operating correctly...):
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#diff --git a/litex/tools/remote/comm_uart.py b/litex/tools/remote/comm_uart.py
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#index bb124fb3..d5a075fd 100644
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#--- a/litex/tools/remote/comm_uart.py
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#+++ b/litex/tools/remote/comm_uart.py
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#@@ -29,6 +29,8 @@ class CommUART(CSRBuilder):
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# if hasattr(self, "port"):
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# return
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# self.port.open()
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#+ for i in range(256):
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#+ self.port.write(0)
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#
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# def close(self):
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# if not hasattr(self, "port"):
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# 4) Start litex_server at 1MBps (CH552 does not seem to work at traditional baudrates...):
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# litex_server --uart --uart-port=/dev/ttyUSBX --uart-baudrate=1000000
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# 5) Test UARTBone ex: litex_cli --regs
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import sipeed_tang_nano
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from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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# Clk / Rst.
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clk24 = platform.request("clk24")
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rst_n = platform.request("user_btn", 0)
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# PLL.
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self.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk24, 24e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCMini):
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def __init__(self, sys_clk_freq=48e6, with_led_chaser=True, **kwargs):
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platform = sipeed_tang_nano.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCMini ----------------------------------------------------------------------------------
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kwargs["uart_name"] = "crossover"
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kwargs["uart_baudrate"] = 1e6 # CH552 firmware does not support traditional baudrates.
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kwargs["with_uartbone"] = True
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SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Nano", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sipeed_tang_nano.Platform, description="LiteX SoC on Tang Nano.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq",default=48e6, type=float, help="System clock frequency.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs")) # FIXME
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if __name__ == "__main__":
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main()
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