89 lines
3.2 KiB
Python
Executable File
89 lines
3.2 KiB
Python
Executable File
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteX-Boards.
|
|
#
|
|
# Copyright (c) 2021 Shinken Sanada <sanadashinken@gmail.com>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
from migen import *
|
|
|
|
from litex.gen import *
|
|
|
|
from litex_boards.platforms import trenz_te0725
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.integration.soc import SoCRegion
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
from litex.soc.cores.led import LedChaser
|
|
|
|
from litex.soc.cores.hyperbus import HyperRAM
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(LiteXModule):
|
|
def __init__(self, platform, sys_clk_freq):
|
|
self.rst = Signal()
|
|
self.cd_sys = ClockDomain()
|
|
|
|
self.pll = pll = S7PLL(speedgrade=-1)
|
|
self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
|
|
pll.register_clkin(platform.request("clk100"), 100e6)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCCore):
|
|
def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
|
|
platform = trenz_te0725.Platform()
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.crg = _CRG(platform, sys_clk_freq)
|
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Trenz TE0725 Board", **kwargs)
|
|
|
|
# Use HyperRAM generic PHY as SRAM ---------------------------------------------------------
|
|
size = int((64*1024*1024) / 8)
|
|
hr_pads = platform.request("hyperram", 0)
|
|
self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
|
|
self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
if with_led_chaser:
|
|
self.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
from litex.build.parser import LiteXArgumentParser
|
|
parser = LiteXArgumentParser(platform=trenz_te0725.Platform, description="LiteX SoC on Trenz TE0725.")
|
|
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
|
|
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
|
|
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(
|
|
sys_clk_freq = args.sys_clk_freq,
|
|
**parser.soc_argdict
|
|
)
|
|
|
|
builder = Builder(soc, **parser.builder_argdict)
|
|
if args.build:
|
|
builder.build(**parser.toolchain_argdict)
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
|
|
|
if args.flash:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="flash"))
|
|
|
|
if __name__ == "__main__":
|
|
main()
|
|
|