mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
245 lines
9.9 KiB
Python
Executable file
245 lines
9.9 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Michael T. Mayers <michael@tweakoz.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import math
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from migen import *
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from litex.build.io import CRG
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from litex_boards.platforms import digilent_nexys4
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc import colorer
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from litex.soc.cores.video import VideoVGAPHY
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from liteeth.phy.rmii import LiteEthPHYRMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain()
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_eth, 50e6)
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# CellularRAM (https://media.digikey.com/PDF/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/MT45W8MW16BGX.pdf)
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class CellularRAM(Module):
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def __init__(self, soc, platform):
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sys_clk_freq = soc.sys_clk_freq
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addr_width = 23
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data_width = 16
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delay_for_70ns = (70e-9) / (1.0/sys_clk_freq)
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delay_for_70ns = int(math.ceil(delay_for_70ns))+1
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#print("sys_clk_freq<%g> delay_for_70ns<%g>\n"%(sys_clk_freq,delay_for_70ns))
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self.bus = wishbone.Interface(data_width=data_width,adr_width=addr_width)
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self.delaycounter = Signal(5)
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cellram = platform.request("cellularram")
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addr = cellram.addr
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data = cellram.data
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wen = cellram.wen
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oen = cellram.oen
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cen = cellram.cen
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clk = cellram.clk
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cre = cellram.cre
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adv = cellram.adv # address valid (low)
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lb = cellram.lb
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ub = cellram.ub
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########################
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tristate_data = TSTriple(data_width)
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self.specials += tristate_data.get_tristate(data)
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########################
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i_rst = ResetSignal("sys")
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fsm = FSM(reset_state="RESET")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.sync += fsm.reset.eq(i_rst)
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########################
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fsm.act("RESET",
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NextState("INIT"))
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########################
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fsm.act("INIT",
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NextValue(self.delaycounter,0),
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NextValue(self.bus.ack,0),
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NextValue(cen,1),
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NextValue(adv,1),
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NextValue(lb,1),
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NextValue(ub,1),
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NextValue(clk,0),
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NextValue(cre,0),
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NextValue(tristate_data.oe,0),
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NextState("IDLE"))
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########################
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fsm.act("IDLE",
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If(self.bus.stb & self.bus.cyc,
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NextValue(lb,~self.bus.sel[0]),
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NextValue(ub,~self.bus.sel[1]),
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NextValue(self.delaycounter,0),
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NextValue(cen,0),
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NextValue(adv,0),
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NextValue(addr,self.bus.adr[:addr_width]),
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If(self.bus.we,
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NextValue(wen,0),
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NextValue(oen,1),
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NextValue(tristate_data.oe,1),
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NextValue(tristate_data.o,self.bus.dat_w[:data_width]),
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NextState("WRITE")
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).Else(
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NextValue(wen,1),
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NextValue(oen,0),
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NextValue(tristate_data.oe,0),
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NextState("READ")
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)
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)
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)
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########################
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fsm.act("WRITE",
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NextValue(self.delaycounter,self.delaycounter+1),
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If(self.delaycounter==delay_for_70ns,
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NextValue(self.bus.ack,1),
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NextState("INIT"))
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)
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########################
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fsm.act("READ",
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NextValue(self.delaycounter,self.delaycounter+1),
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NextValue(self.bus.dat_r,tristate_data.i[:data_width]),
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If(self.delaycounter==delay_for_70ns,
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NextValue(self.bus.ack,1),
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NextState("INIT"))
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)
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########################
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def addCellularRAM(soc, platform, name, origin):
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size = 16*1024*1024
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ram_bus = wishbone.Interface(data_width=soc.bus.data_width)
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ram = CellularRAM(soc,platform)
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soc.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode="rw"))
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soc.check_if_exists(name)
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soc.logger.info("CELLULARRAM {} {} {}.".format(
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colorer(name),
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colorer("added", color="green"),
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soc.bus.regions[name]))
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setattr(soc.submodules, name, ram)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
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platform = digilent_nexys4.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------_-----------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nexys4", **kwargs)
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# Cellular RAM -------------------------------------------------------------------------------
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addCellularRAM(self,platform,"main_ram", 0x40000000)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Nexys4")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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