mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
88 lines
3.6 KiB
Python
Executable file
88 lines
3.6 KiB
Python
Executable file
#!/usr/bin/env python3
|
|
|
|
#
|
|
# This file is part of LiteX-Boards.
|
|
#
|
|
# Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
from migen import *
|
|
from migen.genlib.resetsync import AsyncResetSynchronizer
|
|
|
|
from litex_boards.platforms import ecp5_evn
|
|
|
|
from litex.soc.cores.clock import *
|
|
from litex.soc.integration.soc_core import *
|
|
from litex.soc.integration.builder import *
|
|
from litex.soc.cores.led import LedChaser
|
|
|
|
# CRG ----------------------------------------------------------------------------------------------
|
|
|
|
class _CRG(Module):
|
|
def __init__(self, platform, sys_clk_freq, x5_clk_freq):
|
|
self.rst = Signal()
|
|
self.clock_domains.cd_sys = ClockDomain()
|
|
|
|
# # #
|
|
|
|
# Clk / Rst.
|
|
clk = clk12 = platform.request("clk12")
|
|
rst_n = platform.request("rst_n")
|
|
if x5_clk_freq is not None:
|
|
clk = clk50 = platform.request("ext_clk50")
|
|
self.comb += platform.request("ext_clk50_en").eq(1)
|
|
platform.add_period_constraint(clk50, 1e9/x5_clk_freq)
|
|
|
|
# PLL.
|
|
self.submodules.pll = pll = ECP5PLL()
|
|
self.comb += pll.reset.eq(~rst_n | self.rst)
|
|
pll.register_clkin(clk, x5_clk_freq or 12e6)
|
|
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
|
|
|
# BaseSoC ------------------------------------------------------------------------------------------
|
|
|
|
class BaseSoC(SoCCore):
|
|
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis",
|
|
with_led_chaser=True, **kwargs):
|
|
platform = ecp5_evn.Platform(toolchain=toolchain)
|
|
|
|
# CRG --------------------------------------------------------------------------------------
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
|
|
|
|
# SoCCore ----------------------------------------------------------------------------------
|
|
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECP5 Evaluation Board", **kwargs)
|
|
|
|
# Leds -------------------------------------------------------------------------------------
|
|
if with_led_chaser:
|
|
self.submodules.leds = LedChaser(
|
|
pads = platform.request_all("user_led"),
|
|
sys_clk_freq = sys_clk_freq)
|
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
def main():
|
|
from litex.soc.integration.soc import LiteXSoCArgumentParser
|
|
parser = LiteXSoCArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
|
|
target_group = parser.add_argument_group(title="Target options")
|
|
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
|
|
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
|
|
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
|
|
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
|
|
target_group.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency.")
|
|
builder_args(parser)
|
|
soc_core_args(parser)
|
|
args = parser.parse_args()
|
|
|
|
soc = BaseSoC(toolchain=args.toolchain,
|
|
sys_clk_freq = int(float(args.sys_clk_freq)),
|
|
x5_clk_freq = args.x5_clk_freq,
|
|
**soc_core_argdict(args))
|
|
builder = Builder(soc, **builder_argdict(args))
|
|
builder.build(run=args.build)
|
|
|
|
if args.load:
|
|
prog = soc.platform.create_programmer()
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
|
|
|
|
if __name__ == "__main__":
|
|
main()
|