mirror of
https://github.com/litex-hub/litex-boards.git
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a611f035d6
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical. Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
115 lines
4.7 KiB
Python
Executable file
115 lines
4.7 KiB
Python
Executable file
#!/usr/bin/env python3
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# Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
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# Copyright (c) 2020 Fei Gao <feig@princeton.edu>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex_boards.platforms import vc707
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs):
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platform = vc707.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on VC707", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT8JTF12864(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on VC707")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie_ = args.with_pcie,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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