113 lines
4.1 KiB
Python
Executable File
113 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.official.platforms import genesys2
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41J256M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from liteeth.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys4x.clk.attr.add("keep")
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(125e6), **kwargs):
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platform = genesys2.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41J256M16(self.clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# EthernetSoC ------------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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self.add_csr("ethphy")
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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args = parser.parse_args()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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