154 lines
5.7 KiB
Python
Executable File
154 lines
5.7 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.official.platforms import kcu105
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import EDY4016A
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from litedram.phy import usddrphy
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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from liteeth.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_ic = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys4x.clk.attr.add("keep")
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
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]
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ic_reset_counter = Signal(max=64, reset=63)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(ic_reset_counter != 0,
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ic_reset_counter.eq(ic_reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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ic_rdy = Signal()
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ic_rdy_counter = Signal(max=64, reset=63)
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self.cd_sys.rst.reset = 1
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self.comb += self.cd_ic.clk.eq(self.cd_sys.clk)
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self.sync.ic += [
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If(ic_rdy,
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If(ic_rdy_counter != 0,
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ic_rdy_counter.eq(ic_rdy_counter - 1)
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).Else(
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self.cd_sys.rst.eq(0)
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)
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)
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]
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self.specials += [
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Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE",
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i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset,
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o_RDY=ic_rdy),
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AsyncResetSynchronizer(self.cd_ic, ic_reset)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(125e6), **kwargs):
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platform = kcu105.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_sram_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("USDDRPHY", None)
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sdram_module = EDY4016A(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# EthernetSoC ------------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
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self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
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self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq)
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self.add_csr("ethphy")
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.ethphy.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.cd_eth_rx.clk,
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self.ethphy.cd_eth_tx.clk)
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self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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args = parser.parse_args()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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